Graduate Thesis Or Dissertation
 

System design of a hardware Fortran compiler

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  • This paper describes the system design of a Fortran hardware compiler which converts the original code of a source program into an intermediate code. This code contains features that allow easy machine code generation. An evaluation is first made on the marketability of such a system and then a brief discussion on the features of the intermediate code generated by the hardware compiler. The system is divided into a number of functional blocks. Each block consists of a control unit and a set of hardware logic components. The control unit is realized by Programmable Logic Arrays and all hardware components are state-of-the-art products. Estimates on the typical operating speeds of the functional blocks are made. Flow charts and state diagrams are used to describe the logic flow of the functional blocks.
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  • File scanned at 300 ppi (Monochrome) using Capture Perfect 3.0.82 on a Canon DR-9080C in PDF format. CVista PdfCompressor 4.0 was used for pdf compression and textual OCR.
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