A fast-settling folded-cascode CMOS operational amplifier

Graduate Thesis Or Dissertation

Public Deposited

Citeable URL: https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/7h149s007

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Attribute Name	Values
Creator	Abu-Dayeh, Mahmoud A.
Abstract	A fast-settling CMOS operational amplifier using the folded-cascode topology has been designed. The design is based on a theory developed by Yang et al for the optimum settling time of two-pole systems for switched-capacitor applications. The theory states that the two poles are separated by a given factor in order to obtain a minimum small-signal settling time. The design is achieved by performing a complete small-signal analysis to gain a better understanding of the frequency and time responses of the folded-cascode op-amp. SPICE simulation results are in good agreement with the theoretical predictions.
Resource Type	Masters Thesis
Date Available	2013-06-27T20:54:49+00:00
Date Issued	1988-10-04
Degree Level	Master's
Degree Name	Master of Science (M.S.)
Degree Field	Electrical and Computer Engineering
Degree Grantor	Oregon State University
Commencement Year	1989
Advisor	Allstot, David J.
Committee Member	Plant, Thomas Kiaei, Sayfe Stalley, Robert
Academic Affiliation	Electrical and Computer Engineering
Non-Academic Affiliation	Oregon State University. Graduate School
Subject	Operational amplifiers
Rights Statement	Copyright Not Evaluated
Publisher	Oregon State University
Peer Reviewed	No
Language	English [eng]
Digitization Specifications	File scanned at 300 ppi (Monochrome) using ScandAll PRO 1.8.1 on a Fi-6770A in PDF format. CVista PdfCompressor 5.0 was used for pdf compression and textual OCR.
Replaces	http://hdl.handle.net/1957/39856

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