A subranging analog to digital converter using four bit pipepline

Graduate Thesis Or Dissertation

Public Deposited

Citeable URL: https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/cn69m868z

Descriptions

Attribute Name	Values
Creator	Press, Stephen E.
Abstract	This thesis presents the design of a 10 bit Analog to Digital Converter which consists of a 6 bit flash followed by a 4 bit pipeline architecture. The total system is described and the 4 bit pipeline is implemented on a bipolar process. The objective of this research is to provide an alternative approach to high speed ADC designs and to implement a pipeline ADC which samples at greater speeds than those achieved with presently existing CMOS pipeline designs. This paper presents the complete architecture, the cell design and simulated performance for each block in the pipeline, and the measured results for the four bit pipeline implementation.
Resource Type	Masters Thesis
Date Available	2013-01-10T21:58:36+00:00
Date Issued	1993-01-26
Degree Level	Master's
Degree Name	Master of Science (M.S.)
Degree Field	Electrical and Computer Engineering
Degree Grantor	Oregon State University
Commencement Year	1993
Academic Affiliation	Electrical and Computer Engineering
Non-Academic Affiliation	Oregon State University. Graduate School
Subject	Analog-to-digital converters
Rights Statement	Copyright Not Evaluated
Publisher	Oregon State University
Peer Reviewed	No
Language	English [eng]
Digitization Specifications	File scanned at 300 ppi (Monochrome, 8-bit Grayscale) using ScandAll PRO 1.8.1 on a Fi-6770A in PDF format. CVista PdfCompressor 4.0 was used for pdf compression and textual OCR.
Replaces	http://hdl.handle.net/1957/36065

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