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Filtering by: Creator Al-Alusi, Thamir R. Remove constraint Creator: Al-Alusi, Thamir R. Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science Committee Member Liu, Huaping Remove constraint Committee Member: Liu, Huaping

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  • Low-power dynamic CMOS circuits in high-performance memory arrays

    Creator:
    Patwary, Md. Ataur R.
    Abstract:
    Dynamic CMOS circuits are commonly used in high-performance memory arrays to implement wide-NOR logic functions for their read and search operations. This is because dynamic circuits have significantly higher speed and lower area compared to static circuits for performing similar operations. Register File (RF) arrays are located at the top...
    Resource Type:
    Dissertation
    Full Text:
    AN ABSTRACT OF THE DISSERTATION OF Md. Ataur R. Patwary for the degree of Doctor of Philosophy in

  • Some contributions to asymmetric error control codes

    Creator:
    Elmougy, Samir
    Abstract:
    In some practical systems, most of the errors are of 1 → 0 type and 0 → 1 errors occur very rarely. In this thesis, first, the capacity of the asymmetric channel is derived. The capacity of the binary symmetric channel (BSC) and the Z-channel can be derived from this...
    Resource Type:
    Dissertation
    Full Text:
    errors using r = 2 check bits and up to m2 + r 2 errors using r > 2 check bits. Some upper bound on the

  • A comparative study of lowpass continuous-time delta-sigma modulators with pulse-shaped DACs

    Creator:
    Fang, Jie
    Abstract:
    Recently, continuous-time ΔΣ modulators are appearing increasingly often in both the literature and the marketplace due to their features of inherent antialiasing and relaxed requirements for opamp and so on. However, several nonideal factors such as clock jitter, excess loop delay, inter-symbol interference and so on, degrade the SNR performance...
    Resource Type:
    Masters Thesis
    Full Text:
    feedback DAC from an optimal discrete-time noise transfer function, which can be obtained from R

  • Analysis and modeling of coplanar on-chip interconnects on silicon substrates

    Creator:
    Luoh, Yi
    Abstract:
    The electrical behavior of on-chip interconnects has become a dominant factor in silicon-based high speed, RF, and mixed-signal integrated circuits. In particular, the frequency-dependent loss mechanisms in heavily-doped silicon substrates can have a large influence on the transmission characteristics of on-chip interconnects. To optimize the performance of the integrated circuit,...
    Resource Type:
    Masters Thesis
    Full Text:
    closed-form expressions for the frequency-dependent line parameters R(w), L(w), G(w), and C(w) for

  • Side channel attack resistant elliptic curves cryptosystem on multi-cores for power efficiency

    Creator:
    Yoo, Jaewon
    Abstract:
    The Advent of multi-cores allows programs to be executed much faster than before. Cryptoalgorithms use long-bit words thus parallelizing these operations on multi-cores will achieve significant performance improvement. However, not all long-bit word operations in cryptosystems are suitable for parallel execution on multi-cores. In particular, long-bit words used in Elliptic...
    Resource Type:
    Masters Thesis
    Full Text:
    word multiplication operations are needed for encryption and decryption. J. Fan et al. proposed

  • Urban military operation mobility model

    Creator:
    Kang, Ho Sung
    Abstract:
    A Mobile Ad-hoc NETwork (MANET) is collection of wireless mobile nodes without a network infrastructure or centralized administration. Although MANETs can be used in many applications, such as mobile Internet, military communication, and disaster relief networks, a number of challenges remain. These include routing, medium access control, security, scalability, energy...
    Resource Type:
    Masters Thesis
    Full Text:
    mobility model is needed to appropriately simulate military operations on the battlefield. Hong et al

  • A novel linear generator for wave energy applications

    Creator:
    Ernst, Steven George
    Abstract:
    With the increasing effort to identify alternative methods of energy generation, extraction of ocean energy has gathered a large interest. Research and industry have begun considering wave energy as the next new alternative energy. The unique challenges of ocean energy requires a wave energy converter to be both robust and...
    Resource Type:
    Masters Thesis
    Full Text:
    Magnet Thickness, h (in mm) R e a l P o w e r (W a tt s ) c=1mm c=2mm c=3mm c=4mm c

  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    Energy = Wire Energy (a) R N R R R N 3-cycle 3-cycle 3-cycle 3-cycle Baseline NoC Delay >= 17

  • Information theoretic approach to quantization and classification for signal processing, communications, and machine learning applications

    Creator:
    Thuan Nguyen D.
    Abstract:
    There are five main contributions of this dissertation. The first contribution is new closed-form expressions for channel capacity of a new class of channel matrices. The second contribution is the discovery of the structure for optimal binary quantizer and the associated methods for finding an optimal quantizer that maximizes mutual...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.7.5 Proof of r∗ > 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    usea ‘ready’ (R) bits in the Rename Stage (R-array) and Issue Window to indicate when valid data are