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Filtering by: Committee Member Kimura, Shoichi Remove constraint Committee Member: Kimura, Shoichi Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science License All rights reserved Remove constraint License: All rights reserved

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  • A fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs

    Creator:
    Wang, Xuesheng
    Abstract:
    This thesis proposes a novel fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. The structure of the DAC error is indicated through a simple model for unit-element based DACs. The impact of the DAC error on the performance of ADC is...
    Resource Type:
    Dissertation
    Full Text:
    Mayaram, Prof. Huaping Liu, Prof. Zhongfeng Wang and Prof. Shoichi Kimura for serving in my committee

  • Design techniques for radiation hardened-phase locked loops

    Creator:
    Nemmani, Anantha Nag
    Abstract:
    Spacecrafts experience radiation in the course of their operation and all electronic equipment on board these spacecrafts has to be designed to withstand the effects of this radiation. This thesis describes the effects of total ionization dose (TID) and single event transients (SET) in phase-locked loops - an important circuit...
    Resource Type:
    Masters Thesis

  • A MOSCAP pipeline pseudo passive DAC

    Creator:
    Behera, Prachee Shree
    Abstract:
    The design of a 10-bit pipelined charge redistribution DAC employing MOSCAPs biased in their accumulation mode is presented in this thesis. A switched capacitor filter and output buffer have also been designed for the system. The effect of MOSCAP nonlinearity on the performance of the pipelined charge redistribution DAC has...
    Resource Type:
    Masters Thesis
    Full Text:
    Traylor and Dr. Shoichi Kimura agreed to serve on my examining committee at a short notice, my sincerest

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    , Dr. Thinh Nguyen, and Dr. Shoichi Kimura for serving on my defense committee and for their helpful

  • The commentator information system : understanding journalists' needs to overcome cognitive load and navigation issues

    Creator:
    Midy, Marie-Anne
    Abstract:
    Nowadays, sports events are a significant part of the every-day entertainment with local, national, and international championships. A lot of money is invested by broadcasting companies to attract new and more viewers, acquire broadcasting rights, or send entire crews on site to cover such events. Journalists are among the few...
    Resource Type:
    Masters Thesis
    Full Text:
    thank my committee members: Dr. Margaret Burnett, Dr. Ron Metoyer and Dr. Shoichi Kimura for their

  • Protocol design and optimization for wireless networks

    Creator:
    Lertsutthiwong, Monchai
    Abstract:
    We investigate a number of techniques for increasing throughput and quality of media applications over wireless networks. A typical media communication application such as video streaming imposes strict requirements on the delay and throughout of its packets, which unfortunately, cannot be guaranteed by the underlying wireless network due inherently to...
    Resource Type:
    Dissertation
    Full Text:
    guidance and discussion while working with him. I would like to thank Prof. Sho Kimura for serving on my