This thesis proposes a novel fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. The structure of the DAC error is indicated through a simple model for unit-element based DACs. The impact of the DAC error on the performance of ADC is...
Delta-sigma analog-to-digital converters (ADCs) are suitable for many applications due to several advantages such as relaxed anti-aliasing filter, high signal-to noise and distortion ratio (SNDR) and most important of all, reduced sensitivity to
analog imperfections.This thesis introduces several structures to overcome loop imperfections and stability issues in delta-sigma modulators. First,...
Continues-Time (CT) Delta-Sigma (ΔΣ) Analog-to-Digital Converters (ADCs) have one important constrain, namely the excess loop delay. Most previous excess lop delay compensation methods need to know the exact value of the excess loop delay in advance. However, the value of the excess loop delay is a uniformly distribution random variable....
Two aspects of ADC system performance are addressed in this work. First, the combination of the ADC and its associated reference are co-designed for an energy constrained remote sensing system. Second, sampling linearity is mathematically analyzed as a function of frequency to provide enhanced understanding into an ADC's requisite sampling...
Pipeline analog-to-digital converters (ADCs) have long been used in high-speed systems for power-efficient data conversion. Broadband communication and video processing systems are placing high demands on converter accuracy and speed (above 14 bits and in the multiple-MHz range). The increasing converter requirements coupled with lower supply voltages in modern processes...
VCO-based ADCs have recently emerged as attractive alternative to conventional DeltaSigma (ΔΣ) modulator architectures. Few salient features of a VCObased ADC are: 1) the quantization noise is 1st order noise shaped, 2) it is an open loop architecture, and, 3) its implementation is mostly digital in nature. Hence, they are...
Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data converters which use time based processing. Another artifact of geometry scaling is the increase in complexity of digital circuitry available on traditional analog ICs, as...
Sensors find a variety of applications in portable electronics, automotive and biomedical solutions. The demand for low power and high dynamic range makes the design of digital sensor readout circuits quite challenging. Traditionally, these circuits are realized using amplifiers with passive feedback or precision analog comparators which are power hungry...
Time-domain data conversion has recently drawn increased research attention for its highly digital nature in favor of process technology scaling. Also, as the time information being carried by binary voltage, time-domain operation is much less sensitive to voltage noise compared to conventional voltage domain operation. However, for analog-to-digital converter (ADC)...
This thesis proposes a novel technique for the design of pipelined and cyclic ADCs utilizing generalized radix gain stages. Several models have been proposed for the optimization of high performance pipelined ADCs by various researchers. This work builds upon them, using a simple but accurate model to estimate the optimal...
Delta-sigma analog-to-digital converters traditionally have been used for low speed, high resolution applications such as measurements, sensors, voice and audio systems. Through continued device scaling in CMOS technology and architectural and circuit level design innovations, they have even become popular for wideband, high dynamic range applications such as wired and...
Voltage controlled oscillator (VCO) based ADC is an important class of time-domain ADC that has gained widespread acceptance due to their several desirable properties. VCO-based ADCs behave like an open-loop continuous time ΔΣ modulator and achieve excellent resolution by first order noise shaping the quantization error. However, the SNDR of...
Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical in the development of portable electronic devices with small feature size and long battery life. However, the design of analog and mixed-signal
building blocks, especially...
High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, delta-sigma (ΔΣ) ADCs are able to achieve wide-band operation and...
As CMOS processes keep scaling down devices, the maximum operating frequencies of CMOS devices increase, and hence circuits can process very wide band signals. Moreover, the small physical dimensions of transistors allow the placing of many more blocks into a single chip, including highly accurate analog blocks and complicated digital...
The objective of this work is to explore the feasibility of replacing conventional op-amps with inverters in switched-capacitor (SC) circuits. In order to verify the idea, a low-pass filter (LPF) and a second-order delta-sigma (∆Σ) analog-todigital converter (ADC) are designed in the 0.5-m CMOS technology. The low-pass filter structure is...
As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain...
Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC is limited by the timing accuracy of the sampling clock. A small sampling uncertainty can cause a large error in the sampled voltage and result...
In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and...
In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift the burden of high performance analog circuits from the compressed voltage-domain to the augmented time-domain. First, the potential of high order noise-shaping and phase-domain feedback...
There is a significant need in recent mobile communication and wireless broadband
systems for high-performance analog-to-digital converters (ADCs) that have wide
bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is
recognized as a power-efficient ADC architecture when high resolution (>12-b) is
required. This is due to several advantages...
Nowadays, needs for wideband and high accuracy analog-to-digital converter are increasing rapidly in manifold applications such as wireless communication, digital video and other consumer electronics. Besides, low power consumption is required to have longer battery life in portable systems. CMOS technology scaling and innovative modulator topology make the implementation much...