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Filtering by: Subject Integrated circuits -- Very large scale integration Remove constraint Subject: Integrated circuits -- Very large scale integration Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science

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  • Efficient decoder design for error correction codes

    Creator:
    He, Jinjin
    Abstract:
    Error correction codes (ECCs) have been widely used in communication systems and storage devices. Nowadays, the rapid development of integrated circuit technologies makes feasible the implementation of powerful ECCs such as turbo code and low-density parity-check (LDPC) code. However, these high-performance codes require complex decoding algorithms, resulting in large hardware...
    Resource Type:
    Dissertation
    Full Text:
    systems [1]. Historically, very-large-scale integration (VLSI) technique plays an important role for the

  • Modified VLSI designs for error correction codes

    Creator:
    Chen, Lupin
    Abstract:
    Nowadays, error correction codes have become an integral part in almost all the modern digital communication and storage systems. With the continuously increasing demands for higher speed and lower power communication systems, efficient VLSI implementations of those error correction codes have great importance for practical applications. In this thesis, several...
    Resource Type:
    Masters Thesis
    Full Text:
    my major professor, Dr. Zhongfeng Wang. I feel very honored and privileged to have worked under his

  • TIMR : Time Interleaved Multi Rail

    Creator:
    Ruggeri, Thomas L.
    Abstract:
    This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic supply rails to a circuit. This technique uses the first supply rail to mask the transition delay while changing the voltage of the second rail....
    Resource Type:
    Masters Thesis
    Full Text:
    path of finite resistance from the supply to ground. This finite resistance is very large, but it is

  • Low-complexity high-speed VLSI design of low-density parity-check decoders

    Creator:
    Cui, Zhiqiang
    Abstract:
    Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g.,...
    Resource Type:
    Dissertation
    Full Text:
    complexity of typical decoding algorithm such as MLD becomes very large as codeword length or encoder

  • Efficient VLSI architectures for MIMO and cryptography systems

    Creator:
    Li, Qingwei
    Abstract:
    Multiple-input multiple-output (MIMO) communication systems have recently been considered as one of the most significant technology breakthroughs for modern wireless communications, due to the higher spectral efficiency and improved link reliability. The sphere decoding algorithm (SDA) has been widely used for maximum likelihood (ML) detection in MIMO systems. It is...
    Resource Type:
    Dissertation
    Full Text:
    the emerging standards such as IEEE 802.16. Therefore, the research in the MIMO systems is very