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Filtering by: Subject Pipelined ADCs -- Noise -- Mathematical models Remove constraint Subject: Pipelined ADCs -- Noise -- Mathematical models Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science

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  • Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps

    Creator:
    Gregoire, B. Robert
    Abstract:
    This thesis presents methods to reduce the effects of finite opamp DC gain, output voltage swing limitations in opamps, and component mismatches. The primary contribution of this thesis is a new switched-capacitor method named correlated level shifting (CLS). CLS enables true rail-to-rail operation by storing an estimate of the desired...
    Resource Type:
    Dissertation
    Full Text:
    pipelined ADC performance The previous sections discussed how noise limits performance. The next two

  • Continuous time input pipeline ADCs

    Creator:
    Gubbins, David Patrick
    Abstract:
    Analog-to-digital converters (ADCs) convert analog continuous time signals into discrete time, digital format. One precondition that must be met for conventional nyquist rate ADCs is that the input signal must be suitably band-limited to an input bandwidth less than the nyquist frequency. This mandates expensive anti-alias filters which contribute to...
    Resource Type:
    Dissertation
    Full Text:
    :- sampled opamp noise folding, sampling distortion, re- duced ADC area, switched-capacitor pipeline ADC

  • Low power design techniques for high speed pipelined ADCs

    Creator:
    Lingam, Naga Sasidhar
    Abstract:
    Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters(ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get...
    Resource Type:
    Dissertation
    Full Text:
    asynchronous SAR ADC as the backend of a pipelined ADC to save power. Measurement and simulation results that