Index Catalog // ScholarsArchive@OSU

A comparison of two types of zero-crossing FM demodulators for wireless receivers

Creator:: McNeal, Jeff D.
Abstract:: A comparison of two novel demodulators. The first is a basic zero crossing demodulator, as introduced by Beards. The second is an approach proposed by Hovin. The two demodulators are compared to each other and to the conventional method of demodulation.
Resource Type:: Masters Thesis

Adaptive correction techniques for delta-sigma A/D converters

Creator:: Abdennadher, Salem
Abstract:: Oversampling analog-to-digital and digital-to-analog converters are gaining more popularity in many signal processing applications. Delta-sigma modulators are used in practical applications of oversampling systems because of their apparent practical advantage over other oversampling converters in terms of insensitivity to the inevitable imperfection of the analog circuitry. In Δ∑ modulators, analog...
Resource Type:: Masters Thesis

Adaptive noise cancellation for second-order delta-sigma A/D converters

Creator:: Bribech, Habib
Abstract:: Oversampled analog-to-digital (A/D) converter architectures have been receiving increased attention for high-precision A/D converters. These architectures offer the means of exchanging resolution in time for that in amplitude. Among these oversampled A/D converters, delta-sigma modulators are the most popular method used due to their simplicity in the analog circuitry. The...
Resource Type:: Masters Thesis

Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs

Creator:: Chow, Andrew Siv-Anne
Abstract:: The new CMOS folded source-coupled logic (FSCL) technique intended for mixed-mode integrated circuits has been designed. It has advantages over conventional CMOS circuit in terms of reduced current spike, circuit delay, logic flexibility, and layout density. A simple CPU implemented in 2 μm CMOS technology with a 5.0 volt supply...
Resource Type:: Masters Thesis

CMOS differential logic techniques for mixed-mode applications

Creator:: Chee, San-hwa
Resource Type:: Masters Thesis

Comparison and analysis of current-mode logic circuits with differential and static CMOS

Creator:: Shrivastava, Manu B.
Abstract:: This thesis describes the analysis and comparison of Folded Source-Coupled Logic (FSCL) with standard static CMOS, cascode voltage-switch logic and differential split-level logic gates. The advantages of FSCL are low switching noise and high operating speed. The effect of voltage and device scaling on these topologies is evaluated in terms...
Resource Type:: Masters Thesis

Current-mode flash analog-to-digital converter

Creator:: Maleki, Mohammad
Abstract:: This thesis describes the development of a flash analog-to-digital converter based on current-mode technique. The advantages of current -mode technique are higher speed, smaller chip area, and simple division of reference current based on current mirror. A current-mode comparator is designed consisting of a cascode current mirror and a current...
Resource Type:: Masters Thesis

Design of an asynchronous third-order finite impulse response filter

Creator:: Oren, Joel A.
Abstract:: With the increased demand for complex digital signal processing systems, real-time signal processing requires higher throughput systems. In the past, the throughput has been increased by increasing the clock rates, but synchronization can become increasingly more difficult. Recently there has been renewed interest in designing asynchronous digital systems. In an...
Resource Type:: Masters Thesis

Design of complex digital blocks using folded source-coupled logic for mixed-mode applications

Creator:: Maskai, Sailesh R.
Abstract:: A series of complex digital blocks have been designed and fabricated using the newly developed current-mode differential CMOS logic family viz. the Folded Source-Coupled Logic ( FSCL ). The main feature of this logic family is the low current spikes generated during the switching transitions ( at least 2 orders...
Resource Type:: Masters Thesis

Distributed arithmetic architecture for the discrete cosine transform

Creator:: Poplin, Dwight
Abstract:: The Discrete Cosine Transform is used in many image and video compression standards. Many methods have been developed for efficiently computing the Discrete Cosine Transform including flowgraph algorithms, distributed arithmetic and two-dimensional decompositions. A new architecture based on distributed arithmetic is presented for computing the Discrete Cosine Transform and it's...
Resource Type:: Masters Thesis

Fully efficient pipelined VLSI arrays for solving toeplitz matrices

Creator:: Lee, Louis Wai-Fung
Abstract:: Fully efficient systolic arrays for the solution of Toeplitz matrices using Schur algorithm [1] have been obtained. By applying clustering mapping method [2], the complexity of the algorithm is 0(n) and it requires n/2 processing elements as opposed to n processing elements developed elsewhere [1]. The motivation of this thesis...
Resource Type:: Masters Thesis

Interference cancellation for shot-code DS-CDMA in the presence of channel fading

Creator:: Dutta, Amit K.
Abstract:: Interference from other adjacent users in wireless applications is a major problem in direct-sequence code-division multiple-access (DS-CDMA). This is also known as the near-far problem where a strong signal from one user interferes with other users. The current approach to deal with the near-far problem in DS-CDMA systems is to...
Resource Type:: Dissertation

Low noise FSCL digital circuits for decimation filter

Creator:: Wong, Man Wa
Abstract:: A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed to implement the digital section of mixed-signal IC applications. This FSCL circuit technique offers the advantage of low overlap current spikes during the switching transitions of conventional CMOS gates. This overlap current spike has become one of...
Resource Type:: Masters Thesis

Mapping of recursive algorithms onto multi-rate arrays

Creator:: Zheng, Yue-Peng
Abstract:: In this dissertation, multi-rate array (MRA) architecture and its synthesis are proposed and developed. Using multi-coordinate systems (MCS), a unified theory for mapping algorithms from their original algorithmic specifications onto multi-rate arrays is developed. A multi-rate array is a grid of processors in which each interconnection may have its own...
Resource Type:: Dissertation

Modified conjugate gradient method for ADSL echo cancellation

Creator:: Inoue, Takao
Abstract:: In recent years, high speed data communications over twisted pair cables has gained tremendous demand. Asymmetric Digital Subscriber Line (ADSL) was standardized for use over twisted pair cables. A critical component in ADSL system is the echo canceller which is intended to discriminate unwanted echo signals caused by twisted pair...
Resource Type:: Masters Thesis

New results for differentially detected [pi]/4 DQPSK signal in a direct-conversion transceiver

Creator:: Scarpa, Maxime R.
Resource Type:: Masters Thesis

Optimum equalization and synchronization of broadband multicarrier systems

Creator:: Lashkarian, Navid
Abstract:: The application of information theory and digital signal processing techniques to digital communication has resulted in robust methods for reliable high speed data transmission over noisy channels environments. Among these methods, multicarrier systems have become a viable solution for exploiting maximum spectral efficiency over both wideband highly dispersive static and...
Resource Type:: Dissertation

Scheduling system of affine recurrence equations by means of piecewise affine timing functions

Creator:: Mui, Lap K.
Abstract:: Many systematic methods exist for mapping algorithms to processor arrays. The algorithm is usually specified as a set of recurrence equations, and the processor arrays are synthesized by finding timing and allocation functions which transform index points in the recurrences into points in a space-time domain. The problem of scheduling...
Resource Type:: Masters Thesis

Sensitivity analysis and architectural comparison of narrow-band sharp-transition digital filters

Creator:: Kulkarni, Satish S.
Abstract:: Due to advances in high-density low-cost VLSI and communication technology, digital filtering and signal processing are being widely used for real-time signal processing applications. Given the filter specification, choosing the best filter structure for a given application is not a trivial task. The choice of a particular filter structure depends...
Resource Type:: Masters Thesis

Synthesis of multi-rate arrays from directional uniform recurrence equations

Creator:: Li, Aihua
Abstract:: Advances in VLSI array processing have led to many new parallel structures for real-time Digital Signal Processing (DSP) applications. Among all the architectures, systolic arrays have played an important role because systolic arrays have regular, local interconnections with modular structure. In ordinary systolic arrays, however, all processing operations and data...
Resource Type:: Masters Thesis

VLSI implementation of adaptive BIT/serial IIR filters

Creator:: Badyal, Rajeev
Abstract:: A new structure for the implementation of bit/serial adaptive IIR filter is presented. The bit level system consists of gated full adders for the arithmetic unit and data latches for the data path. This approach allows recursive operation of the IIR filter to be implemented without any global interconnections, minimal...
Resource Type:: Masters Thesis

ScholarsArchive@OSU

A comparison of two types of zero-crossing FM demodulators for wireless receivers

Adaptive correction techniques for delta-sigma A/D converters

Adaptive noise cancellation for second-order delta-sigma A/D converters

Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs

CMOS differential logic techniques for mixed-mode applications

Comparison and analysis of current-mode logic circuits with differential and static CMOS

Current-mode flash analog-to-digital converter

Design of an asynchronous third-order finite impulse response filter

Design of complex digital blocks using folded source-coupled logic for mixed-mode applications

Distributed arithmetic architecture for the discrete cosine transform

Fully efficient pipelined VLSI arrays for solving toeplitz matrices

Interference cancellation for shot-code DS-CDMA in the presence of channel fading

Low noise FSCL digital circuits for decimation filter

Mapping of recursive algorithms onto multi-rate arrays

Modified conjugate gradient method for ADSL echo cancellation

New results for differentially detected [pi]/4 DQPSK signal in a direct-conversion transceiver

Optimum equalization and synchronization of broadband multicarrier systems

Scheduling system of affine recurrence equations by means of piecewise affine timing functions

Sensitivity analysis and architectural comparison of narrow-band sharp-transition digital filters

Synthesis of multi-rate arrays from directional uniform recurrence equations

VLSI implementation of adaptive BIT/serial IIR filters

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