Index Catalog // ScholarsArchive@OSU

VLSI implementation of adaptive BIT/serial IIR filters

Creator:: Badyal, Rajeev
Abstract:: A new structure for the implementation of bit/serial adaptive IIR filter is presented. The bit level system consists of gated full adders for the arithmetic unit and data latches for the data path. This approach allows recursive operation of the IIR filter to be implemented without any global interconnections, minimal...
Resource Type:: Masters Thesis

Synthesis of multi-rate arrays from directional uniform recurrence equations

Creator:: Li, Aihua
Abstract:: Advances in VLSI array processing have led to many new parallel structures for real-time Digital Signal Processing (DSP) applications. Among all the architectures, systolic arrays have played an important role because systolic arrays have regular, local interconnections with modular structure. In ordinary systolic arrays, however, all processing operations and data...
Resource Type:: Masters Thesis

Sensitivity analysis and architectural comparison of narrow-band sharp-transition digital filters

Creator:: Kulkarni, Satish S.
Abstract:: Due to advances in high-density low-cost VLSI and communication technology, digital filtering and signal processing are being widely used for real-time signal processing applications. Given the filter specification, choosing the best filter structure for a given application is not a trivial task. The choice of a particular filter structure depends...
Resource Type:: Masters Thesis

Scheduling system of affine recurrence equations by means of piecewise affine timing functions

Creator:: Mui, Lap K.
Abstract:: Many systematic methods exist for mapping algorithms to processor arrays. The algorithm is usually specified as a set of recurrence equations, and the processor arrays are synthesized by finding timing and allocation functions which transform index points in the recurrences into points in a space-time domain. The problem of scheduling...
Resource Type:: Masters Thesis

Resolution enhancement of analog-to-digital converters through computationally simple digital filtering

Creator:: Zahl, Eric L.
Abstract:: The resolution of analog-to-digital converters can be distinguished as absolute resolution, or average resolution. This study reviews average resolution enhancement techniques and proposes a method which is particularly applicable as a low-cost modification to a high-speed waveform acquisition system. This method uses oversampling combined with computationally simple digital filtering to...
Resource Type:: Masters Thesis

Power spectrum estimation of sinusoids from white and colored noises using the canonical correlation analysis method

Creator:: Luo, Lei
Abstract:: The purpose of this thesis is to apply the Canonical Correlation Analysis (CCA) which belongs to the parametric methods for power spectral estimation in the environments of either white noise or colored noise. It is shown that optimal state space variables belong to the range space of the canonical vectors...
Resource Type:: Masters Thesis

New results for differentially detected [pi]/4 DQPSK signal in a direct-conversion transceiver

Creator:: Scarpa, Maxime R.
Resource Type:: Masters Thesis

Modified conjugate gradient method for ADSL echo cancellation

Creator:: Inoue, Takao
Abstract:: In recent years, high speed data communications over twisted pair cables has gained tremendous demand. Asymmetric Digital Subscriber Line (ADSL) was standardized for use over twisted pair cables. A critical component in ADSL system is the echo canceller which is intended to discriminate unwanted echo signals caused by twisted pair...
Resource Type:: Masters Thesis

Low noise FSCL digital circuits for decimation filter

Creator:: Wong, Man Wa
Abstract:: A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed to implement the digital section of mixed-signal IC applications. This FSCL circuit technique offers the advantage of low overlap current spikes during the switching transitions of conventional CMOS gates. This overlap current spike has become one of...
Resource Type:: Masters Thesis

Fully efficient pipelined VLSI arrays for solving toeplitz matrices

Creator:: Lee, Louis Wai-Fung
Abstract:: Fully efficient systolic arrays for the solution of Toeplitz matrices using Schur algorithm [1] have been obtained. By applying clustering mapping method [2], the complexity of the algorithm is 0(n) and it requires n/2 processing elements as opposed to n processing elements developed elsewhere [1]. The motivation of this thesis...
Resource Type:: Masters Thesis

ScholarsArchive@OSU

VLSI implementation of adaptive BIT/serial IIR filters

Synthesis of multi-rate arrays from directional uniform recurrence equations

Sensitivity analysis and architectural comparison of narrow-band sharp-transition digital filters

Scheduling system of affine recurrence equations by means of piecewise affine timing functions

Resolution enhancement of analog-to-digital converters through computationally simple digital filtering

Power spectrum estimation of sinusoids from white and colored noises using the canonical correlation analysis method

New results for differentially detected [pi]/4 DQPSK signal in a direct-conversion transceiver

Modified conjugate gradient method for ADSL echo cancellation

Low noise FSCL digital circuits for decimation filter

Fully efficient pipelined VLSI arrays for solving toeplitz matrices

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