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Filtering by: Creator Chinnayakanahalli, Kiran J. Remove constraint Creator: Chinnayakanahalli, Kiran J. Academic Affiliation Electrical and Computer Engineering Remove constraint Academic Affiliation: Electrical and Computer Engineering

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  • Design methodology for low-jitter phase-locked loops

    Creator:
    Bhagavatheeswaran, Shanthi, S.
    Abstract:
    This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case)...
    Resource Type:
    Masters Thesis
    Full Text:
    Hamm, Kiran Gullappalli, and David Fitts. I would like to thank Nathen Barton and Aline Sadate for

  • The architecture of a multimedia multiprocessor

    Creator:
    Choi, Keung-Sik
    Abstract:
    The multimedia capabilities of computers have recently become the focus of computer developers due to the increasing demand for advanced computer graphics and new media capabilities, such as video conferencing, 3-D visualization, and animation. To support these multimedia capabilities, specialized graphics hardware, such as MPEG encoding/decoding card, 3-D graphics card,...
    Resource Type:
    Masters Thesis