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  • Design strategies for interface of bus architectures

    Creator:
    Nayak, Harish Chandra B.
    Abstract:
    This paper discusses the design strategies for interface of bus architectures. It also describes the design of interface between the two popular bus architectures, the Micro Channel and the Nu Bus. The main objective of this thesis is to develop a procedure for bus interface design and use this procedure...
    Resource Type:
    Masters Thesis
    Full Text:
    Computer Engineering presented on August 7. 1989 Title : Design Strategies for the Interface of Bus

  • A microarchitecture study of the counterflow pipeline principle

    Creator:
    Janik, Kenneth J.
    Abstract:
    The counterflow pipeline concept was originated by Sproull et. al.[1] to demonstrate the concept of asynchronous circuits. The basic premise is that a simple architecture with only local communication and control and a simple regular structure will result in increased performance. This thesis attempts to analyze the performance of the...
    Resource Type:
    Dissertation
    Full Text:
    Electrical and Computer Engineering presented on February 27th, 1998. Title: A Microarchitecture Study of

  • Fine-grain parallelism on sequential processors

    Creator:
    Kotikalapoodi, Sridhar V.
    Abstract:
    There seems to be a consensus that future Massively Parallel Architectures will consist of a number nodes, or processors, interconnected by high-speed network. Using a von Neumann style of processing within the node of a multiprocessor system has its performance limited by the constraints imposed by the control-flow execution model....
    Resource Type:
    Masters Thesis
    Full Text:
    Computer Engineering presented on September 7. 1994. Title: FineGrain Parallelism On Sequential Processors

  • The dynamic simultaneous multithreaded processor

    Creator:
    Ortiz-Arroyo, Daniel
    Abstract:
    This dissertation investigates diverse techniques to support multithreading in modern high performance processors. The mechanisms studied expand the architecture of a high performance superscalar processor to control efficiently the interaction between software-controlled and hardware-controlled multithreading. Additionally, dynamic speculative mechanisms are proposed to exploit thread-level-parallelism (TLP) and instruction-level-parallelism (ILP) on a...
    Resource Type:
    Dissertation
    Full Text:
    4.1 Simulation Tools in Computer Architecture

  • Reduced instruction set computer memory architectures

    Creator:
    Widjaja, Stephen
    Abstract:
    This thesis describes the design of a Reduced Instruction Set Computer. Its instruction memory utilizes a unique cache architecture and a two-stage memory pipelining technique. Because of the bandwidth of the 64-bit instruction bus, instruction prefetching is possible and is implemented. The data memory is bridged by a four-way set-associative...
    Resource Type:
    Masters Thesis
    Full Text:
    Set Computer. Its instruction memory utilizes a unique cache architecture and a two-stage memory

  • Allocation of SISAL program graphs to processors using BLAS

    Creator:
    Raisinghani, Manoj H.
    Abstract:
    There are a number of well known techniques for extracting parallelism from a given program. They range from hardware implementations, building restructuring compilers or reorganizing of programs so as to specify all the available parallelism. The success rate of any of the known techniques is rather poor over all types...
    Resource Type:
    Masters Thesis
    Full Text:
    system. Here the target architecture is a simulated nCUBE 3E computer, having a hypercube topology

  • The design of a reduced instruction set computer using a silicon compiler

    Creator:
    Zhang, Licheng
    Abstract:
    The objective of this thesis is to describe the design and implementation of a VSLI reduced instruction set computer (RISC). The RISC machine constitutes a new style of computer architecture. It differs significantly from the complex instruction set computer architectures (CISC) of the past. RISC architectures are characterized by their...
    Resource Type:
    Masters Thesis
    Full Text:
    computer (RISC). The RISC machine constitutes a new style of computer architecture. It differs

  • A new RISC architecture for high speed data acquisition

    Creator:
    Gribble, Donald L.
    Abstract:
    This thesis describes the design of a RISC architecture for high speed data acquisition. The structure of existing data acquisition systems is first examined. An instruction set is created to allow the data acquisition system to serve a wide variety of applications. The architecture is designed to allow the execution...
    Resource Type:
    Masters Thesis
    Full Text:
    and Computer Engineering presented on November 12, 1991. Title: A New RISC Architecture for High

  • CounterDataFlow architecture : design and performance

    Creator:
    Miller, Michael F., (Michael Frederic)
    Abstract:
    The counterflow pipeline concept was originated by Sproull and Sutherland to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making and localized clocking and data movement. We have taken these ideas and reformulated them into a substantially faster more scalable architecture that has the same distributed...
    Resource Type:
    Masters Thesis

  • A programmable network interface unit for hybrid meshnet local area networks

    Creator:
    Merchant, Shashank C.
    Abstract:
    A Hybrid Meshnet LAN, a new local area network architecture, has been proposed by Dr. Cheoul-Shin Kang and Dr. James Herzog. It provides for distributed control hybrid architecture which is good for effective load sharing under various local area network environments. Hybrid Meshnet has a dual channel structure, a token...
    Resource Type:
    Masters Thesis
    Full Text:
    Science in Electrical and Computer Engineering presented on June 4, 1992. Title: A Programmable Network