Index Catalog // ScholarsArchive@OSU

Creator:: Galli, Reto
Abstract:: Several papers propose the use of on-line arithmetic for signal processing applications implemented on FPGAs. Although those papers provide reasonable arguments for the use of on-line arithmetic, they give only inadequate or incomplete comparisons of the proposed on-line designs to other state of the art solutions on FPGAs. In this...
Resource Type:: Masters Thesis
Full Text:: Evaluation of On-line Arithmetic Modules and Networks for Signal Processing Applications on FPGAs. Abstract

Creator:: Myers, Timothy F.
Abstract:: A new algorithm is proposed which provides a sub-optimum near-far resistant pattern for correlation with a known signal in a spread-spectrum multiple access environment with additive white gaussian noise (AWGN). Only the patterns and respective delays of the K-1 interfering users are required. The technique does not require the inversion...
Resource Type:: Masters Thesis
Full Text:: correlator to be implementable in VLSI technology. This approach allows processing of the received signal in

Creator:: Huster, Carl R.
Abstract:: The parallelization and vectorization of Monte Carlo algorithms for modelling charge transport in semiconductor devices are considered. The standard ensemble Monte Carlo simulation of a three parabolic band model for GaAs is first presented as partial verification of the simulation. The model includes scattering due to acoustic, polar-optical and intervalley...
Resource Type:: Masters Thesis
Full Text:: A parallel/vector Monte Carlo MESFET model for

Creator:: Mui, Lap K.
Abstract:: Many systematic methods exist for mapping algorithms to processor arrays. The algorithm is usually specified as a set of recurrence equations, and the processor arrays are synthesized by finding timing and allocation functions which transform index points in the recurrences into points in a space-time domain. The problem of scheduling...
Resource Type:: Masters Thesis
Full Text:: affect the implementation of the processing element. The DG also imposes certain precedence constraints

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