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Filtering by: Creator Kurnosov, V. B. Remove constraint Creator: Kurnosov, V. B. Committee Member Liu, Huaping Remove constraint Committee Member: Liu, Huaping

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  • Design techniques for low-voltage and low-power analog-to-digital converters

    Creator:
    Ahn, Gil Cho
    Abstract:
    With the ever-increasing demand for portable devices used in applications such as wireless communication, mobile computing, consumer electronics, etc., the scaling of the CMOS process to deep submicron dimensions becomes more important to achieve low-cost, low-power and high-performance digital systems. However, this downscaling also requires similar shrinking of the supply...
    Resource Type:
    Dissertation
    Full Text:
    -digital converters. To demonstrate the proposed design techniques, a 0.6 V, 82 dB, 2-2 cascaded au- dio

  • An enhanced swing differential Colpitts CMOS VCO for low-voltage operation

    Creator:
    Farahbakhshian, Farhad
    Abstract:
    An enhanced swing differential Colpitts VCO (ESDC-VCO) dramatically improves the swing of a Colpitts VCO by allowing the signal to swing below ground and above the supply voltage. Fabricated in a 1P8M 0.13 um CMOS process, the ESDC-VCO operates at 4.9GHz with a 0.475-V supply and consumes 2.7mW. The measured...
    Resource Type:
    Masters Thesis
    Full Text:
    o is e d B c/ H z V DD = 475mV FIGURE 4.2: Measured phase noise of ESDC-VCO. TABLE

  • Ultra-low power receivers for wireless sensor networks

    Creator:
    Ayers, James S.
    Abstract:
    In wireless sensor network applications, low-power operation of the wireless receiver is critical. To address this need an ultra-low power Binary Frequency Shift Keying (BFSK) receiver using the super-regenerative architecture is developed. A prototype receiver is built and tested for operation in the 900 MHz ISM band. Lab measurements show...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . 10 2.2 Recent Low Power Receivers. Component Key: L=LNA, M=Mixer, V=VCO, FD=Freq. Divider, B=LO

  • Low-power design techniques for low-voltage analog-to-digital converters

    Creator:
    Kim, Min Gyu
    Abstract:
    The demand for portable electronic systems and the continued down-scaling of device dimensions resulted in rapid improvement in the performance of integrated systems. Several low-voltage design techniques have been proposed to operate analog circuits with sub-1V supply. However, these techniques require higher power consumption to achieve large dynamic range while...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.10 (a) SNR vs. input level; (b) SNDR vs. input level for a 0.9 V supply voltage

  • Evaluation of partial discharge in inverter driven medium voltage propulsion coils

    Creator:
    Ramme, André
    Abstract:
    Advancements in power electronics to higher power levels and faster switching times allow new machine and systems designs, but also create higher stresses on electric machinery insulation. High performance, pulse-width modulated (PWM) inverters are now available for medium voltage drive systems, and are being considered by the U.S. Navy as...
    Resource Type:
    Dissertation
    Full Text:
    representative propulsion coils employing two different 4160 V insulation systems and were evaluated by both an

  • High efficiency delta-sigma modulation data converters

    Creator:
    Lee, Kyehyung
    Abstract:
    Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. Integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common...
    Resource Type:
    Dissertation
    Full Text:
    state-of-the-art prototype designs: (1) a 0.8 V, 2.6 mW, 88 dB dual-channel audio delta-sigma

  • Power Efficient Architectures for Low Noise Switched-Capacitor Filters and High Accuracy Analog-to-Digital Converters

    Creator:
    Payandehnia, Pedram
    Abstract:
    Filters and data converters are key analog-and-mixed-signal (AMS) building blocks in communication systems, such as software-defined radios and internet-of-things. In this dissertation, novel switched-capacitor filter and analog-to-digital converter (ADC) circuit configurations have been explored which are power efficient and are digital scaling friendly. First, a novel switched-capacitor low-pass filter architecture...
    Resource Type:
    Dissertation
    Full Text:
    mW from a 1.8 V supply. Next, an opamp-free noise shaping successive-approximation register (SAR

  • RF and Millimeter-wave Techniques to Improve Scalability and Efficiency of Digital Beamforming Arrays

    Creator:
    Johnson, Manoj
    Abstract:
    Spectrum overcrowding, ever increasing demand for high data rate and increased mobility requirements are three major challenges 5G-technology is trying to address. In this thesis I start with a RF front-end technique that deals with blocker interference arising from spectrum overcrowding both across frequency bands and within the same frequency...
    Resource Type:
    Dissertation
    Full Text:
    by, F = 1 + v∗2n,sw v∗2n,a + v∗2n,sh v∗2n,a ( Ra +Rsw Rsh )2 + v∗2n,B v∗2n,a ( Ra +Rsw γRB )2

  • Design and analysis techniques for nano-joule ADCs and sampling linearity

    Creator:
    Brown, Thomas (Thomas William)
    Abstract:
    Two aspects of ADC system performance are addressed in this work. First, the combination of the ADC and its associated reference are co-designed for an energy constrained remote sensing system. Second, sampling linearity is mathematically analyzed as a function of frequency to provide enhanced understanding into an ADC's requisite sampling...
    Resource Type:
    Dissertation
    Full Text:
    . 8 Table 1.1: Micro-Power ADCs Ref. Power BW ENOB Vdd E/bit∗ Process Architecture (µW) (kHz) (b) (V

  • Design techniques for low-power multi-GS/s analog-to-digital converters

    Creator:
    Jiang, Tao
    Abstract:
    Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off...
    Resource Type:
    Dissertation
    Full Text:
    previous work of sub-ADC, a 12-GS/s 5-b 50-mW ADC is designed in 40nm CMOS with 8 time-interleaved