In this paper, an analysis of the clock-feedthrough effects in
switched-current (SI)' circuits will be presented. The clock-feedthrough
effects caused by the non-ideal characteristic of MOS
switches when they are turned off limit the accuracy of the analog
track-and-hold (T/H) circuits. A model to analyze and characterize this
effect is...
Advancements in the sophistication and complexity of modern electronic systems are creating a need for highly integrated systems with ever higher operational frequencies. The economical demands of these systems dictate that they be implemented using low cost fabrication technologies, such as digital CMOS. One of the major challenges facing circuit...
This thesis will examine the model and design technique of a self-contained analog
CMOS Phase-Locked Loop. This system has an adaptable filter and demodulator for an
oscillating frequency of up to 1000 KHz and it is programmable by means of an external
resistor and capacitor. The first topic to be...
The gm/ID-based design of analog integrated circuits introduced in 1996 employs an empirical transistor sizing methodology using SPICE-generated lookup tables that enables good agreement between simulations and specifications. This thesis introduces a new SPICE lookup table that extends the gm/ID approach to the Miller pole-splitting frequency compensation of the classical...
The CMOS two-stage Operational Transconductance Amplifier (OTA) has been a key enabler for mixed-signal IC design for nearly four decades . This research focuses on a modified two-stage CMOS OTA that features load-pole cancellation (LPC); i.e., the resulting architecture is essentially a two-stage CMOS OTA with no load capacitance. The...
Multi-level decision feedback equalization (MDFE) is an effective sampled signal processing technique to remove inter-symbol interference (ISI) from disk read-back signals. Parallelism which doubles the symbol rate can be realized by utilizing the characteristic of channel response and decision feedback equalization algorithm.
A mixed-signal IC implementation has been chosen for...
A frequency compensation technique for increasing the
settling speed of two-stage operational amplifiers used in
switched-capacitor applications has been developed. By
properly decompressing the pole-zero doublet to form a
three-pole one zero system, the settling speed is increased
up to 50 percent as compared to the optimized two-pole
system.
Digitally-programmable filters have been an ongoing research topic for a number of years. The first such filters were FIR transversal filters using Charge-Coupled Devices (CCD's) and IIR recursive filters using switched-capacitor (SC) techniques. Although both techniques achieve excellent results, they require non-standard and/or additional IC fabrication steps. Low substrate doping...
A MOS biquadratic (biquad) filter employing the switched-current technique is
reported. The circuit uses current-mode processing which can offer wide
bandwidth, low voltage operation, and can be implemented with standard CMOS
technology. Examples of lowpass, highpass, and bandpass filters are given
which illustrate the synthesis procedures and the versatility of...