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Filtering by: Creator Owens, Brian E. Remove constraint Creator: Owens, Brian E. Advisor Fiez, Terri S. Remove constraint Advisor: Fiez, Terri S. Creator Bhagavatheeswaran, Shanthi, S. Remove constraint Creator: Bhagavatheeswaran, Shanthi, S.

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  • Design methodology for low-jitter phase-locked loops

    Creator:
    Bhagavatheeswaran, Shanthi, S.
    Abstract:
    This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case)...
    Resource Type:
    Masters Thesis
    Full Text:
    Kiyong, Srinath, Praveen, Ramana Aisola, Gary, Jim, Wade, Dave, Brian, Ling, Bob Garbs, Bob Rice, Steve