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Filtering by: Creator Surya, Vinay N. Remove constraint Creator: Surya, Vinay N. Advisor Fiez, Terri S. Remove constraint Advisor: Fiez, Terri S.

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  • Design of current-mode track and hold circuits

    Creator:
    Chennam, Madhusudhan
    Abstract:
    A differential current-mode track-and-hold (T/H) amplifier is used to sample an analog input signal. A new closed-loop current-mode architecture has been developed that overcomes the stability problems associated with closed-loop architectures. The T/H circuit has been fabricated in a 0.35-μm quad-metal, double-poly CMOS process. The measured total harmonic distortion (THD)...
    Resource Type:
    Masters Thesis
    Full Text:
    Nilakantan Seshan, Vinay Chandrasekar, Kalyan Ghatak, Yemelong Constand, Prashanth Drakshapalli, Taras Dudar

  • A substrate noise coupling model for lightly doped CMOS processes

    Creator:
    Sadate, Aline C.
    Abstract:
    This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...
    Resource Type:
    Masters Thesis
    Full Text:
    measure- ments, Vinay Chandrasekhar and Nathen Barton for the rides at odd hours of the night. I

  • Design of a variable gain, high linearity, low power baseband filter for WLAN transmitters

    Creator:
    Ranganathan, Sachin
    Abstract:
    A variable gain, high linearity, low power baseband filter for WLAN applications is implemented in a 1.5 V 3 V 0.15 μm CMOS process. This fourth-order low-pass filter, which is introduced in the transmit channel as a reconstruction filter between the D/A converter and the mixer, has a measured cut-off...
    Resource Type:
    Masters Thesis
    Full Text:
    , Zhimin, Volodymyr, Taras, Chenggang, Yutao, Shengjun, Kalyan, Vinay, Ravikanth, Ajit and Patrick for the

  • Design methodology for low-jitter phase-locked loops

    Creator:
    Bhagavatheeswaran, Shanthi, S.
    Abstract:
    This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case)...
    Resource Type:
    Masters Thesis
    Full Text:
    all their help and friendship. Thanks to Tina Batten, Vinay Chandra.sekhar, Taras Dudar, Christina

  • Design of sample and holds using CCDs in a standard CMOS process

    Creator:
    Ghatak, Kalyan Brata
    Abstract:
    The parasitic components of MOS switches at high speeds affect the linearity and resolution of CMOS sample and hold circuits. CCD-based circuit design can offer good performance at high speeds. This thesis presents the design of sample and hold circuits using charge-coupled device structures in a standard CMOS process. Three...
    Resource Type:
    Masters Thesis
    Full Text:
    , Prashanth Drakshapalli, Kannan Soundarapandian, Sachin Ranganathan and oth- ers. I also thank Vinay

  • Prediction of phase noise and jitter in ring oscillators

    Creator:
    Barton, Nathen
    Abstract:
    This thesis presents distinctly different methods of accurately predicting phase noise and absolute jitter in ring oscillators. The phase noise prediction methods are the commercially available SpectreRF and isf_tool, a simulator developed in this work from the Hajimiri and Lee theory of phase noise. Absolute jitter due to deterministic supply...
    Resource Type:
    Masters Thesis
    Full Text:
    whom to work with and learn from. Without the direct peer review of Nilakantan Seshan and Vinay

  • Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

    Creator:
    Sharma, Ajit
    Abstract:
    This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate...
    Resource Type:
    Masters Thesis
    Full Text:
    , Mohana, Trimmy, Vinay, Sharath, Nimish, Shuba, Gautham, Vivek, Pavan, Manas, Manu, Laddu, Triet, YuHua

  • Design of a 1.8-V 14-bit [delta] - [sigma] A/D converter with 8X oversampling and 4 MHz Nyquist output rate

    Creator:
    Jiang, Ruoxin
    Abstract:
    In this dissertation, a new Δ∑ A/D converter is presented that is ideally suited for communication applications. It is based on a single-loop single-stage structure, which can realize a high maximum out-of-band quantization noise gain while maintaining stable operation and thus achieve 14-bit resolution at 8 times oversampling. A fifth-order...
    Resource Type:
    Dissertation
    Full Text:
    thank Aline Sadate, Vinay Chandrasekhar, Madhusudhan Chennam, Yemelong Constand, Taras Dudar, Yutao Hu