A new structure for the implementation of bit/serial adaptive IIR filter is
presented. The bit level system consists of gated full adders for the arithmetic
unit and data latches for the data path. This approach allows recursive
operation of the IIR filter to be implemented without any global
interconnections, minimal...
Advances in VLSI array processing have led to many new
parallel structures for real-time Digital Signal Processing (DSP)
applications. Among all the architectures, systolic arrays have played
an important role because systolic arrays have regular, local
interconnections with modular structure. In ordinary systolic arrays,
however, all processing operations and data...
Due to advances in high-density low-cost VLSI and communication technology,
digital filtering and signal processing are being widely used for real-time signal processing
applications. Given the filter specification, choosing the best filter structure for a given
application is not a trivial task. The choice of a particular filter structure depends...
Many systematic methods exist for mapping algorithms to processor arrays. The algorithm is usually specified as a set of recurrence equations, and the processor arrays are synthesized by finding timing and allocation functions which transform index points in the recurrences into points in a space-time domain. The problem of scheduling...
The application of information theory and digital signal processing techniques to digital
communication has resulted in robust methods for reliable high speed data transmission
over noisy channels environments. Among these methods, multicarrier systems have
become a viable solution for exploiting maximum spectral efficiency over both wideband
highly dispersive static and...
In recent years, high speed data communications over twisted pair cables has gained
tremendous demand. Asymmetric Digital Subscriber Line (ADSL) was standardized for
use over twisted pair cables. A critical component in ADSL system is the echo canceller
which is intended to discriminate unwanted echo signals caused by twisted pair...
In this dissertation, multi-rate array (MRA) architecture and its synthesis are proposed
and developed. Using multi-coordinate systems (MCS), a unified theory for mapping
algorithms from their original algorithmic specifications onto multi-rate arrays is
developed.
A multi-rate array is a grid of processors in which each interconnection may have its
own...
A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed
to implement the digital section of mixed-signal IC applications. This FSCL circuit technique
offers the advantage of low overlap current spikes during the switching transitions
of conventional CMOS gates. This overlap current spike has become one of...
Interference from other adjacent users in wireless applications is a major problem
in direct-sequence code-division multiple-access (DS-CDMA). This is also known as the
near-far problem where a strong signal from one user interferes with other users. The
current approach to deal with the near-far problem in DS-CDMA systems is to...