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Filtering by: Subject Integrated circuits -- Very large scale integration Remove constraint Subject: Integrated circuits -- Very large scale integration Advisor Kiaei, Sayfe Remove constraint Advisor: Kiaei, Sayfe

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  • Mapping of recursive algorithms onto multi-rate arrays

    Creator:
    Zheng, Yue-Peng
    Abstract:
    In this dissertation, multi-rate array (MRA) architecture and its synthesis are proposed and developed. Using multi-coordinate systems (MCS), a unified theory for mapping algorithms from their original algorithmic specifications onto multi-rate arrays is developed. A multi-rate array is a grid of processors in which each interconnection may have its own...
    Resource Type:
    Dissertation
    Full Text:
    performance computing can be achieved by using application specific computers that utilize Very-Large-Scale

  • Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs

    Creator:
    Chow, Andrew Siv-Anne
    Abstract:
    The new CMOS folded source-coupled logic (FSCL) technique intended for mixed-mode integrated circuits has been designed. It has advantages over conventional CMOS circuit in terms of reduced current spike, circuit delay, logic flexibility, and layout density. A simple CPU implemented in 2 μm CMOS technology with a 5.0 volt supply...
    Resource Type:
    Masters Thesis
    Full Text:
    . The mixed-mode analog/digital integrated circuit has not only provided high integration, but also

  • Design of complex digital blocks using folded source-coupled logic for mixed-mode applications

    Creator:
    Maskai, Sailesh R.
    Abstract:
    A series of complex digital blocks have been designed and fabricated using the newly developed current-mode differential CMOS logic family viz. the Folded Source-Coupled Logic ( FSCL ). The main feature of this logic family is the low current spikes generated during the switching transitions ( at least 2 orders...
    Resource Type:
    Masters Thesis
    Full Text:
    from National Science Foundation Center for the Design of Analog-Digital Integrated Circuits (CDADIC

  • Fully efficient pipelined VLSI arrays for solving toeplitz matrices

    Creator:
    Lee, Louis Wai-Fung
    Abstract:
    Fully efficient systolic arrays for the solution of Toeplitz matrices using Schur algorithm [1] have been obtained. By applying clustering mapping method [2], the complexity of the algorithm is 0(n) and it requires n/2 processing elements as opposed to n processing elements developed elsewhere [1]. The motivation of this thesis...
    Resource Type:
    Masters Thesis
    Full Text:
    decreased by factor of 2. The efficiency is n+1 E 2n-1 For very large number of n, E will be close to 1