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  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    and Computer Engineering presented on September 21, 2006. Title: Single-Level Dynamic Register

  • The dynamic speculation and performance prediction of parallel loops

    Creator:
    Zier, David A.
    Abstract:
    General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any...
    Resource Type:
    Dissertation
    Full Text:
    in Electrical and Computer Engineering presented on May 1, 2009. Title: The Dynamic Speculation and

  • Porting GCC to X32V architecture

    Creator:
    Venkatachalapathy, Savithri H.
    Abstract:
    This thesis work evaluates the need for a re-configurable cross compiler for the X32V processor architecture and discusses the process of developing a cross compiler for X32V. X32V is a new processor intended at the embedded applications domain whose instruction set is designed based on the widely used MIPS processor....
    Resource Type:
    Masters Thesis

  • Development and evaluation of X32V

    Creator:
    Hong, Jumnit
    Abstract:
    Embedded processors are utilized in many applications with considerable time spent developing and maintaining functionality and performance. Performance being a key factor in adding features such as video and audio to a product. Configurable processors, such as X32V, allow the addition of functionality and performance without large increases in design...
    Resource Type:
    Masters Thesis

  • Fine-grain parallelism on sequential processors

    Creator:
    Kotikalapoodi, Sridhar V.
    Abstract:
    There seems to be a consensus that future Massively Parallel Architectures will consist of a number nodes, or processors, interconnected by high-speed network. Using a von Neumann style of processing within the node of a multiprocessor system has its performance limited by the constraints imposed by the control-flow execution model....
    Resource Type:
    Masters Thesis
    Full Text:
    Computer Engineering presented on September 7. 1994. Title: FineGrain Parallelism On Sequential Processors

  • Allocation of SISAL program graphs to processors using BLAS

    Creator:
    Raisinghani, Manoj H.
    Abstract:
    There are a number of well known techniques for extracting parallelism from a given program. They range from hardware implementations, building restructuring compilers or reorganizing of programs so as to specify all the available parallelism. The success rate of any of the known techniques is rather poor over all types...
    Resource Type:
    Masters Thesis
    Full Text:
    system. Here the target architecture is a simulated nCUBE 3E computer, having a hypercube topology