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Filtering by: Creator Han, Myung Woo Advisor Lee, Il Beom

Multithreaded virtual processor on DSM

Creator:

An, Ho Seok

Abstract:

Modern superscalar processors exploit instruction-level parallelism (ILP) by issuing multiple instructions in a single cycle because of increasing demand for higher performance in computing. However, stalls due to cache misses severely degrade the performance by disturbing the exploitation of ILP. Multiprocessors also greatly exacerbate the memory latency problem. In SMPs,...

Resource Type:

Masters Thesis

Full Text:

. Burton. I am also grateful to Dr. Han Tak Kwak for answering many questions about the details of the
Eager data transfer mechanism for user-level network protocol

Creator:

Won, Chulho

Abstract:

This dissertation investigates the use of a hardware mechanism called Eager Data Transfer (EDT) for achieving the reduction of communication latency for user-level network protocol. To reach the goal, the dissertation addresses the following research issues. First, the development of a communication system performance evaluation tool called Linux/SimOS is presented....

Resource Type:

Dissertation

Full Text:

colleagues at ETRI have provided valuable advice and support during my study. I like to thank Dr. Woo-Jong
The dynamic simultaneous multithreaded processor

Creator:

Ortiz-Arroyo, Daniel

Abstract:

This dissertation investigates diverse techniques to support multithreading in modern high performance processors. The mechanisms studied expand the architecture of a high performance superscalar processor to control efficiently the interaction between software-controlled and hardware-controlled multithreading. Additionally, dynamic speculative mechanisms are proposed to exploit thread-level-parallelism (TLP) and instruction-level-parallelism (ILP) on a...

Resource Type:

Dissertation