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Filtering by: Creator Kamvar, Z. N. Remove constraint Creator: Kamvar, Z. N. Advisor Mayaram, Kartikeya Remove constraint Advisor: Mayaram, Kartikeya Contributor advisor sim Moon, Un-Ku Remove constraint Contributor advisor sim: Moon, Un-Ku

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  • Design techniques for radiation hardened-phase locked loops

    Creator:
    Nemmani, Anantha Nag
    Abstract:
    Spacecrafts experience radiation in the course of their operation and all electronic equipment on board these spacecrafts has to be designed to withstand the effects of this radiation. This thesis describes the effects of total ionization dose (TID) and single event transients (SET) in phase-locked loops - an important circuit...
    Resource Type:
    Masters Thesis
    Full Text:
    blocks is explained in the following section. CTRLPFD + TDC N LF(z) Digital Loop Filter DCAO

  • Digital phase-locked loops for multi-GHz clock generation

    Creator:
    Kratyuk, Volodymyr
    Abstract:
    A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved...
    Resource Type:
    Dissertation
    Full Text:
    gain of the CPPLL in Fig. 2.4 is given by: LG(s) = ICP 2π KV CO s 1 N s + ωz s R (2.7) where ωz

  • Design techniques for PVT tolerant phase-locked loops

    Creator:
    Wu, Ting
    Abstract:
    The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
    Resource Type:
    Dissertation
    Full Text:
    G(s) = ICP 2π R(1 + ωz s ) Ko s 1 N = ωc(1 + ωz s ) 1 s (2.10) where ωc is defined by Eq

  • Oscillators and phase locked loops for space radiation environments

    Creator:
    Vandepas, Martin
    Abstract:
    Circuits operating outside the earth’s atmosphere are more vulnerable to cosmic radiation and require special design consideration. The purpose of this work is to explore methods of mitigating the effect of radiation in phase locked loop (PLL) circuits. Several voltage controlled oscillators (VCOs) and two complete PLLs are designed and...
    Resource Type:
    Masters Thesis
    Full Text:
    2.5 300 400 500 600 700 800 900 1000 1100 1200 Control Voltage (V) Fr eq ue n cy (M H z

  • Automated analysis, design, and optimization of low noise oscillators

    Creator:
    Vytyaz, Igor
    Abstract:
    Low noise oscillators are universally needed in digital systems for clock generation and synchronization, and in radio-frequency communication front-ends for frequency up- and down-conversion. Noise in oscillators results in timing jitter, and limits the clock frequency of digital systems. In radio-frequency communication systems, phase noise in oscillators lowers the signal-to-noise...
    Resource Type:
    Dissertation
    Full Text:
    numbers are the iteration count N DEC and N S of the PSS-DEC anal- ysis and the search-based method

  • A stochastic time-to-digital converter for digital phase-locked loops

    Creator:
    Ok, Kerem
    Abstract:
    Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter...
    Resource Type:
    Masters Thesis
    Full Text:
    . PFD + TDC ÷ N LF(z) Digital Loop Filter DCAO �in �out 9 The resolution of the