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Filtering by: Advisor Mayaram, Kartikeya Remove constraint Advisor: Mayaram, Kartikeya Committee Member Hanumolu, Pavan Remove constraint Committee Member: Hanumolu, Pavan Decade 2000-2009 Remove constraint Decade: 2000-2009

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  • Substrate noise coupling in ring oscillator-based phase locked loops

    Creator:
    Shreeve, Robert
    Abstract:
    In this thesis, the performance degradation of a phase-locked loop due to substrate noise is examined. A new analytical equivalent circuit model for substrate noise coupling is derived for a heavily doped silicon substrate. The model has been validated with measured data from a 0.35 μm CMOS process. Since the...
    Resource Type:
    Masters Thesis

  • Design techniques for PVT tolerant phase-locked loops

    Creator:
    Wu, Ting
    Abstract:
    The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
    Resource Type:
    Dissertation