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Filtering by: Advisor Mayaram, Kartikeya Committee Member Traylor, Roger Decade 2000-2009

Substrate coupling macromodel for lightly doped CMOS processes

Creator:

Koteeswaran, Mohanalakshmi

Abstract:

A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of...

Resource Type:

Masters Thesis
Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits

Creator:

Hanken, Christopher

Abstract:

Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This...

Resource Type:

Masters Thesis
Digital phase-locked loops for multi-GHz clock generation

Creator:

Kratyuk, Volodymyr

Abstract:

A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved...

Resource Type:

Dissertation