Index Catalog // ScholarsArchive@OSU

Ultra-low energy digital logic controller design for wireless sensor networks

Creator:: Meliza, Stephen W.
Abstract:: Low energy design techniques for digital circuits are examined to determine their suitability for use in a digital logic controller for wireless sensor network nodes. Transistor level simulations are used to evaluate the techniques and those demonstrating an energy reduction are used to implement a digital logic controller. The digital...
Resource Type:: Masters Thesis

An ultra low voltage micropower GPS receiver RF front-end for wildlife tracking

Creator:: Heiberg, Adam C.
Abstract:: A fully integrated CMOS GPS receiver RF front end optimized for low power operation is presented. The system operates with a supply voltage down to 250 mV. A prototype has been fabricated in a 0.13μm CMOS process and includes a low voltage LNA, quadrature oscillators, and quadrature mixers. It exhibits...
Resource Type:: Masters Thesis

Substrate noise coupling in ring oscillator-based phase locked loops

Creator:: Shreeve, Robert
Abstract:: In this thesis, the performance degradation of a phase-locked loop due to substrate noise is examined. A new analytical equivalent circuit model for substrate noise coupling is derived for a heavily doped silicon substrate. The model has been validated with measured data from a 0.35 μm CMOS process. Since the...
Resource Type:: Masters Thesis

A nano-power wake-up circuit for RF energy harvesting wireless sensor networks

Creator:: Lindsley, Christopher J.
Abstract:: A fully integrated CMOS latched comparator is presented for use as a wake-up circuit that is attached to an RF energy harvester in a battery free wireless sensor network. The system consumes less than 36nA static current at 20°C and dissipates 2pJ of energy per conversion. The comparator comprises of...
Resource Type:: Masters Thesis

Digital phase-locked loops for multi-GHz clock generation

Creator:: Kratyuk, Volodymyr
Abstract:: A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved...
Resource Type:: Dissertation

Analysis and design of CMOS RF LNAs with ESD protection

Creator:: Chandrasekhar, Vinay
Abstract:: An analysis that accounts for the effect of standard electrostatic discharge (ESD) structures on critical LNA specifications of noise figure, input matching and gain is presented. It is shown that the ESD structures degrade LNA performance particularly for higher frequency applications. Two LNAs, one with ESD protection and one without,...
Resource Type:: Masters Thesis

Accurate and efficient simulation of synchronous digital switching noise in system on a chip

Creator:: Habal, Husni
Abstract:: A new method is presented to compress switching information in large digital circuits. This is combined with an efficient approach of generating the noise signatures of cells in a digital library that results in an accurate and efficient approach for estimating the noise generated in digital circuits. This method provides...
Resource Type:: Masters Thesis

Frequency domain steady-state simulation of oscillators

Creator:: Duan, Xiaochun
Abstract:: The focus of this work is on developing algorithms for frequency domain steady-state analysis of oscillators. Convergence problems associated with the frequency domain harmonic balance simulation of oscillators have been examined. Globally convergent homotopy methods have been combined with the harmonic balance method for robust high-Q oscillator simulation. Various homotopy...
Resource Type:: Dissertation

A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's

Creator:: Hazenboom, Duncan S.
Abstract:: Three types of low noise amplifiers operating at 2.4GHz were designed. They are the commonly used single-ended and differential amplifiers as well as a new quasi-differential amplifier. The substrate noise injected into these amplifiers is examined for both heavily and lightly doped CMOS substrates. For the single-ended amplifier the noise...
Resource Type:: Masters Thesis

Computationally efficient substrate noise coupling estimation in lightly doped silicon substrates

Creator:: Srinivasan, Kavitha
Abstract:: A Z-parameter based macromodel for characterizing the substrate noise coupling in a lightly doped substrate at low frequencies has been developed. The model is scalable with contact geometries and separation. The cross-coupling impedance between two contacts is modeled using an improved geometric mean distance formulation. This approach obviates the need...
Resource Type:: Masters Thesis

ScholarsArchive@OSU

Ultra-low energy digital logic controller design for wireless sensor networks

An ultra low voltage micropower GPS receiver RF front-end for wildlife tracking

Substrate noise coupling in ring oscillator-based phase locked loops

A nano-power wake-up circuit for RF energy harvesting wireless sensor networks

Digital phase-locked loops for multi-GHz clock generation

Analysis and design of CMOS RF LNAs with ESD protection

Accurate and efficient simulation of synchronous digital switching noise in system on a chip

Frequency domain steady-state simulation of oscillators

A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's

Computationally efficient substrate noise coupling estimation in lightly doped silicon substrates

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