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Filtering by: Creator Klimley, A. Peter Remove constraint Creator: Klimley, A. Peter Advisor Moon, Un Ku Remove constraint Advisor: Moon, Un Ku Advisor Mayaram, Kartikeya Remove constraint Advisor: Mayaram, Kartikeya

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  • Design techniques for PVT tolerant phase-locked loops

    Creator:
    Wu, Ting
    Abstract:
    The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
    Resource Type:
    Dissertation
    Full Text:
    significantly increased. As a result, the performance of PLLs that are susceptible to process, voltage, and