Search Constraints

Start Over
Filtering by: Creator Kamvar, Z. N. Remove constraint Creator: Kamvar, Z. N. Advisor Moon, Un Ku Remove constraint Advisor: Moon, Un Ku Contributor advisor sim Moon, Un-Ku Remove constraint Contributor advisor sim: Moon, Un-Ku

Search Results

  • A Wide Modulation Range and PVT-Tolerant Spread-Spectrum Modulation Clock Generator

    Creator:
    Sun, Hyuk
    Abstract:
    This dissertation presents a phase domain in-loop-bandwidth spread-spectrum clock generation technique. In this proposed technique, a charge-based discrete-time loop filter is proposed to enable the phase domain in-loop-bandwidth spread-spectrum modulation without a delta-sigma modulator or time-to-digital converter. The in-loop-bandwidth modulation technique maximizes the loop bandwidth to improve phase noise suppression...
    Resource Type:
    Dissertation
    Full Text:
    3.1 z-Domain Model

  • Architectural compensation techniques for analog inaccuracies in delta-sigma analog-to-digital converters, Architectural compensation techniques for analog inaccuracies in ΔΣanalog-to-digital converters

    Creator:
    Maghari, Nima
    Abstract:
    Delta-sigma analog-to-digital converters (ADCs) are suitable for many applications due to several advantages such as relaxed anti-aliasing filter, high signal-to noise and distortion ratio (SNDR) and most important of all, reduced sensitivity to analog imperfections.This thesis introduces several structures to overcome loop imperfections and stability issues in delta-sigma modulators. First,...
    Resource Type:
    Dissertation
    Full Text:
    function of Hi(z) = bi · z−1 1− z−1 (2.4) 10 X 1H (z) 2H (z) nH (z) SLY 1E 1Q 1a 2a n 1a − na qV (z

  • A multi-bit hybrid DSM over full-scale range without feedback DEM

    Creator:
    Kwon, Sunwoo, 1974-
    Abstract:
    Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a ∆Σ ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) ∆Σ Modulator (∆ΣM) is inadequate for low-power wideband applications...
    Resource Type:
    Dissertation
    Full Text:
    different 14 H(s) H(z) xCT(t)=0 YCT xDT(t)=0 YDT DAC DAC TS vCT(n) vDT(n) H(z)DAC vDT(n)H(s)DAC

  • Design techniques for radiation hardened-phase locked loops

    Creator:
    Nemmani, Anantha Nag
    Abstract:
    Spacecrafts experience radiation in the course of their operation and all electronic equipment on board these spacecrafts has to be designed to withstand the effects of this radiation. This thesis describes the effects of total ionization dose (TID) and single event transients (SET) in phase-locked loops - an important circuit...
    Resource Type:
    Masters Thesis
    Full Text:
    blocks is explained in the following section. CTRLPFD + TDC N LF(z) Digital Loop Filter DCAO

  • High-speed switched-capacitor filters based on unity-gain buffers

    Creator:
    Bruneau, David
    Abstract:
    In this work a new voltage buffer, the drain-follower, achieves 300MHz band-width with 2pF load, a dc gain of 0.993V/V, 1mV offset voltage, -60 dB total harmonic distortion at 1.4Vpp output voltage and 6.5mW power dissipation from 5V supply. A unity-gain buffer switched-capacitor biquad filter has been implemented in 0.5μm...
    Resource Type:
    Masters Thesis
    Full Text:
    Improvement ................... 9 2.3 The PMOS source-follower with N-Well Buffer ....................... 11

  • Design of low OSR, high precision analog-to-digital converters

    Creator:
    Rajaee, Omid
    Abstract:
    Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited...
    Resource Type:
    Dissertation
    Full Text:
    -1 MASH is as following D1 = Xin + (1− z −1)E1 (2.3) D2 = −HF1E1 + (1− z − 1 N )E2 (2.4) Y

  • Low voltage switched capacitor circuits for lowpass and bandpass [delta sigma] converters

    Creator:
    Keskin, Mustafa
    Abstract:
    The most accurate method for performing analog signal processing in MOS (metal-oxide-semiconductor) integrated circuits is through the use of switched-capacitor circuits. A switched-capacitor circuit operates as a discrete-time signal processor. These circuits have been used in a variety of applications, such as filters, gain stages, voltage-controlled oscillators, and modulators. A...
    Resource Type:
    Dissertation
    Full Text:
    55 3.5 Pseudo-N-Path Resonators ................... 56 3.5.1 Finite Opamp-Gain Effects for PNP

  • An efficient switched capacitor buck-boost voltage regulator using delta-sigma control loop

    Creator:
    Rao, Arun
    Abstract:
    Voltage converters or charge pumps find their use in many circuits. They are extensively used in hand held devices as cell phones, pagers, PDA's and laptops. Some of the important issues relating to design of voltage regulators for handheld devices are size, efficiency and noise. Another important factor to be...
    Resource Type:
    Masters Thesis
    Full Text:
    possible gain settings 3 bits are e(n) 1 u(n) >® > H(z) > > y(n) x(n) Figure 5.1. Linear model of a L

  • Efficient use of time information in analog-to-digital converters

    Creator:
    Hu, Yue
    Abstract:
    Time-domain data conversion has recently drawn increased research attention for its highly digital nature in favor of process technology scaling. Also, as the time information being carried by binary voltage, time-domain operation is much less sensitive to voltage noise compared to conventional voltage domain operation. However, for analog-to-digital converter (ADC)...
    Resource Type:
    Dissertation
    Full Text:
    Filtering Vin(t) Fout[n] Ref N-Stage Ring Oscillator 1-Z -1 Sample D A C E le m e n t Barrel

  • Digital phase-locked loops for multi-GHz clock generation

    Creator:
    Kratyuk, Volodymyr
    Abstract:
    A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved...
    Resource Type:
    Dissertation
    Full Text:
    gain of the CPPLL in Fig. 2.4 is given by: LG(s) = ICP 2π KV CO s 1 N s + ωz s R (2.7) where ωz