Search Constraints

Start Over
Filtering by: Alternative title ssim FS 69 Remove constraint Alternative title ssim: FS 69 Advisor Moon, Un Ku Remove constraint Advisor: Moon, Un Ku

Search Results

  • A multi-bit hybrid DSM over full-scale range without feedback DEM

    Creator:
    Kwon, Sunwoo, 1974-
    Abstract:
    Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a ∆Σ ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) ∆Σ Modulator (∆ΣM) is inadequate for low-power wideband applications...
    Resource Type:
    Dissertation
    Full Text:
    integrator (blue dotted). Opamp GBW is normalized to sampling frequency, FS

  • Continuous time input pipeline ADCs

    Creator:
    Gubbins, David Patrick
    Abstract:
    Analog-to-digital converters (ADCs) convert analog continuous time signals into discrete time, digital format. One precondition that must be met for conventional nyquist rate ADCs is that the input signal must be suitably band-limited to an input bandwidth less than the nyquist frequency. This mandates expensive anti-alias filters which contribute to...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.13 Power Breakdown of the prototype ADC . . . . . . . . . . . . . . . 69 4.1 Optimized

  • Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters

    Creator:
    Guerber, Jon
    Abstract:
    In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and...
    Resource Type:
    Dissertation
    Full Text:
    ................................................................... 69 Figure 3.36: TSAR die photo along with calibration and full-chip views

  • Automated synthesis of analog to digital conversion

    Creator:
    Weaver, Skyler
    Abstract:
    This thesis describes circuit architectures and techniques that facilitate the automatic synthesis and fabrication of analog-to-digital converters (ADCs). Since automated synthesis already exists for digital circuits and is part of the digital circuit design flow, this work demonstrates the feasibility of ADC synthesis with little or no modification to presently...
    Resource Type:
    Dissertation
    Full Text:
    of 1 MHz sine input. fS = 8 MHz. b) Measured transfer function of the same parallel comparators as

  • Efficient use of time information in analog-to-digital converters

    Creator:
    Hu, Yue
    Abstract:
    Time-domain data conversion has recently drawn increased research attention for its highly digital nature in favor of process technology scaling. Also, as the time information being carried by binary voltage, time-domain operation is much less sensitive to voltage noise compared to conventional voltage domain operation. However, for analog-to-digital converter (ADC)...
    Resource Type:
    Dissertation
    Full Text:
    Figure 3.35: Measured output spectrum with -3dBFS signal at 210kHz. .................... 69 (Frequency

  • Low-power design techniques for low-voltage analog-to-digital converters

    Creator:
    Kim, Min Gyu
    Abstract:
    The demand for portable electronic systems and the continued down-scaling of device dimensions resulted in rapid improvement in the performance of integrated systems. Several low-voltage design techniques have been proposed to operate analog circuits with sub-1V supply. However, these techniques require higher power consumption to achieve large dynamic range while...
    Resource Type:
    Dissertation
    Full Text:
    . The factor OSR is referred to as the oversampling ratio (OSR), OSR = fs/2fB. Fig. 3.3 (a) and (b) are

  • Limitations and optimization of a blind calibration algorithm for nonlinearity in analog to digital converters

    Creator:
    Coker, Brandilyn
    Abstract:
    Analog to digital converters (ADCs) are a critical part of communication between the physical world and the increasingly digital systems humans use every day. ADCs have inherent non-idealities that degrade performance. Nonlinearity is one of the most prevalent non-idealities that designers face. While calibration methods for nonlinearity exist in the...
    Resource Type:
    Masters Thesis
    Full Text:
    , i.e. f < 0.50fs, and thus one of the frequencies ”folds” around fs and appears to be a different

  • Design techniques for low-voltage and low-power analog-to-digital converters

    Creator:
    Ahn, Gil Cho
    Abstract:
    With the ever-increasing demand for portable devices used in applications such as wireless communication, mobile computing, consumer electronics, etc., the scaling of the CMOS process to deep submicron dimensions becomes more important to achieve low-cost, low-power and high-performance digital systems. However, this downscaling also requires similar shrinking of the supply...
    Resource Type:
    Dissertation
    Full Text:
    6.1 Performance summary of the prototype pipelined ADC.. . . . . . . . . . 69 To my parents Haesook

  • Ring amplification for switched capacitor circuits

    Creator:
    Hershberg, Benjamin Poris
    Abstract:
    A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.4.2 Implementation Details

  • Power-Efficient Design Techniques and Architectures for Scalable Submicron Analog Circuits

    Creator:
    Xu, Yang
    Abstract:
    As the CMOS process scales down to submicron, digital circuit performance improves, while reduced supply voltage and lower transistor intrinsic gain make it difficult to implement analog circuits in a power efficient manner. Therefore, it has become advantageous to shift more analog signal processing functions conventionally realized in voltage (analog)...
    Resource Type:
    Dissertation
    Full Text:
    Circuit Implementation ……………………………………………..…….. 68 4.4.1 ΔΣ Modulator …………………………………………….………. 69 4.4.2