The demand for portable electronic systems and the continued
down-scaling of device dimensions resulted in rapid improvement in
the performance of integrated systems. Several low-voltage design
techniques have been proposed to operate analog circuits with sub-1V
supply. However, these techniques require higher power consumption
to achieve large dynamic range while...
This thesis proposes a novel technique for the design of pipelined and cyclic ADCs utilizing generalized radix gain stages. Several models have been proposed for the optimization of high performance pipelined ADCs by various researchers. This work builds upon them, using a simple but accurate model to estimate the optimal...
Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a ∆Σ ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) ∆Σ Modulator (∆ΣM) is inadequate for low-power wideband applications...
Pipeline analog-to-digital converters (ADCs) have long been used in high-speed systems for power-efficient data conversion. Broadband communication and video processing systems are placing high demands on converter accuracy and speed (above 14 bits and in the multiple-MHz range). The increasing converter requirements coupled with lower supply voltages in modern processes...
Multi-stage delta-sigma (ΔΣ) architectures, commonly known as MASH, are the preferred choice for analog-to-digital converters (ADCs) used in broadband communication applications, where high-resolution (above 14 bits) and high-bandwidth (several MHz) performances are required. Current state-of-the-art designs are capable of as much as 5-MS/s output data rates with 90-dB SNR. However,...
Spacecrafts experience radiation in the course of their operation
and all electronic equipment on board these spacecrafts has to
be designed to withstand the effects of this radiation.
This thesis describes the effects of total ionization dose (TID)
and single event transients (SET) in phase-locked loops - an
important circuit...
Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter...
A radix-based calibration technique was previously proposed with a two-stage algorithmic analog-to-digital converter (ADC). The objective of this work is to verify the capability of radix-based calibration for a true multi-stage ADC. In order to prove the idea, a single bit-per-stage, 20-stage pipelined ADC is designed in a 0.35-μm CMOS...
As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain...
Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low-voltage conditions. There are several well-known techniques to bypass the problem. These approaches include: (1)...