Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance analog-to-digital conversion combined with very low power consumption. This dissertation presents two different approaches to achieving high power efficiency from a two-step pipelined architecture, which...
This work presents a high-resolution Delta-Sigma ADC which combines the use of the pseudo-pseudo-differential noise filtering technique with single-ended ring amplifier based integrators. The pseudo-pseudo-differential noise filtering technique utilizes single-ended circuits while maintaining the even-order rejection found in fully-differential structures which alleviates, in the active analog blocks, the need for...
Successive-approximation-register (SAR) analog-to-digital converters are popular for medium accuracy, medium speed and low power applications, such as in biomedical applications. They have low latency and simple architecture compared with ΔΣ ADCs. This is because of SAR ADCs’ binary searching scheme. Furthermore, SAR ADCs can apply oversampling and noise shaping schemes...
Low noise oscillators are universally needed in digital systems for clock generation and synchronization, and in radio-frequency communication front-ends for frequency up- and down-conversion. Noise in oscillators results in timing jitter, and limits the clock frequency of digital systems. In radio-frequency communication systems, phase noise in oscillators lowers the signal-to-noise...
Ring amplification has emerged as an efficient technique to drive large capacitive loads in switched capacitor circuits. We propose circuit techniques to demonstrate the first application of a ring amplifier in a non-capacitive feedback system of a LDO. These techniques enable a simple cap-less LDO structure in 180nm CMOS that...
To realize pipelined ADCs in deep-submicron processes, low voltage techniques
must be developed to work around problems created by limited supply voltages such as
the floating switch dead zone, reduced SNR, and reduced OpAmp performance.
This thesis analyzes standard and low voltage design issues for pipelined ADCs
and proposes a...
In recent years, SAR ADCs have been shown to acheive faster conversion times and improved power efficiencies due to their simple building blocks that are digital in nature and scale favorably with technology. High resolution ADCs with stringent noise requirement has led to the adoption of hybrid ADC architectures such...
With the ever-increasing demand for portable devices used in applications
such as wireless communication, mobile computing, consumer electronics, etc.,
the scaling of the CMOS process to deep submicron dimensions becomes more
important to achieve low-cost, low-power and high-performance digital systems.
However, this downscaling also requires similar shrinking of the supply...
The demand for portable electronic systems and the continued
down-scaling of device dimensions resulted in rapid improvement in
the performance of integrated systems. Several low-voltage design
techniques have been proposed to operate analog circuits with sub-1V
supply. However, these techniques require higher power consumption
to achieve large dynamic range while...
Data converters are ubiquitous building blocks of a signal chain. The rapid increase in
communication and connectivity devices presents new avenues for pushing the state of
the art analog to digital converters. Techniques for improving resolution, bandwidth,
linearity and bit-error rate, while reducing the power, energy and area is the...