Search Constraints

Start Over
Filtering by: Creator Keller%2C Aimee A. Remove constraint Creator: Keller%2C Aimee A. Advisor Temes, Gabor C. Remove constraint Advisor: Temes, Gabor C.

Search Results

  • A 10 bit algorithmic A/D converter for a biosensor

    Creator:
    Rengachari, Thirumalai
    Abstract:
    This thesis presents a novel algorithmic A/D converter to be used in a biosensor. The converter is capable of a conversion rate of 1.5 bits/phase and hence the required conversion time is reduced. The proposed architecture is analyzed for non-ideal effects and compared with existing algorithmic A/D architectures. The converter...
    Resource Type:
    Masters Thesis
    Full Text:
    . Title: A 10 Bit Algorithmic A/D Converter for a Bio-sensor Abstract approved: Gabor C. Temes and Un-Ku

  • Low-voltage pipeline A/D converter

    Creator:
    Wu, Lei
    Abstract:
    Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor (SC) circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low voltage conditions. There exist three techniques to solve the problem, but with their...
    Resource Type:
    Masters Thesis
    Full Text:
    tovcc switch network Cmoonl A to n cD I gnd gndl CSA S4A cD2 voutp S3 CS = 2C Cmoon 1

  • Compensation techniques for cascaded delta-sigma A/D converters and high-performance switched-capacitor circuits

    Creator:
    Sun, Tao
    Abstract:
    This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC circuits. A CDS technique...
    Resource Type:
    Dissertation
    Full Text:
    Compensation Techniques for Cascaded Delta-Sigma A/D

  • High-linearity switched-capacitor circuits in digital CMOS technologies

    Creator:
    Yoshizawa, Hirokazu
    Abstract:
    In this thesis, novel design techniques have been proposed for implementing high-linearity SC circuits in a standard digital CMOS process. They use nonlinear MOSFET capacitors instead of linear double-poly capacitors. To reduce their nonlinearities, a bias voltage is applied to keep MOSFET capacitors in their accumulation regions. For further reduction...
    Resource Type:
    Dissertation
    Full Text:
    thesis, novel design techniques have been proposed for implementing high- linearity SC circuits in a

  • Design techniques for low power ADCs

    Creator:
    Yu, Wenhuan
    Abstract:
    This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the noise performance of the incremental ADC, and a new optimization technique was proposed to minimize the output noise. In the calibration mode, the incremental ADC...
    Resource Type:
    Dissertation
    Full Text:
    converter (DAC) mismatch correction. A theoretical time- domain analysis technique was developed to predict

  • Design techniques for low power high speed successive approximation analog-to-digital converters

    Creator:
    Lin, Jiaming
    Abstract:
    This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the...
    Resource Type:
    Dissertation
    Full Text:
    compared to 2NBIT*Cu in the traditional SAR. In a C-2C capacitor ladder, the actual ratio of the

  • Low-voltage data converters

    Creator:
    Meng, Qingdong
    Abstract:
    With the growing demand for portable/consumer electronics, such as digital audio/video (AV), the downscaling of device dimensions, which enables the integration of an increasing number of transistors in a single chip, is mandatory. This trend also continuously pushes the power supply voltage down to reduce the power consumption and improve...
    Resource Type:
    Dissertation
    Full Text:
    number of transistors in a single chip, is mandatory. This trend also continuously pushes the power

  • Noise coupling techniques in multi-cell delta-sigma modulators

    Creator:
    Bonu, Madhulatha
    Abstract:
    High performance multi-cell delta-sigma modulators are a preferred choice in applications which require programmability. Multi-cell delta-sigma modulators with M unit cells provide 10log10(M) SQNR improvement for the same thermal noise and bias power due to the uncorrelated quantization noises of the M unit ADCs. This concept is used in this...
    Resource Type:
    Masters Thesis
    Full Text:
    : ______________________________________________________ Gabor C. Temes High performance multi-cell delta-sigma modulators are a preferred choice

  • Low-Power 12-bit Quasi-Passive Segmented DAC Implemented in 130nm CMOS Technology

    Creator:
    Pierce, Alexander G.
    Abstract:
    This thesis work proposes a low-power 12-bit digital-to-analog converter (DAC) designed in a 130nm process. The DAC to be presented is of a segmented design where the architecture is split into pipelined and thermometer coded segments. This allows for high linearity and low distortion while maintaining high speed and low...
    Resource Type:
    Masters Thesis
    Full Text:
    on a capacitor it has a voltage difference equal to ∆𝑉 = 𝑊𝐿𝐶!F(𝑉GG − 𝑉1+ − 𝑉HI) 2𝐶

  • Low-power successive approximation analog to digital converter with digital calibration

    Creator:
    Li, Wei
    Abstract:
    IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This...
    Resource Type:
    Dissertation
    Full Text:
    dissertation is focused on a low-power 12-bit 12.5- MS/s successive approximation (SAR) ADC with a couple of