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Filtering by: Creator Karmarkar, Vidyadhar M. Remove constraint Creator: Karmarkar, Vidyadhar M. Advisor Weisshaar, Andreas Remove constraint Advisor: Weisshaar, Andreas

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  • Metal fill considerations for on-chip interconnects and spiral inductors

    Creator:
    Shilimkar, Vikas S.
    Abstract:
    Variability in circuit performance due to process defects is a major concern in integrated circuit (IC) fabrication. Advanced IC manufacturing processes employ Chemical-Mechanical Polishing (CMP) for planarization of oxide and metal layers. CMP defects result in variations in the oxide and metal topographical profile. To reduce these topographical variations, electrically...
    Resource Type:
    Masters Thesis
    Full Text:
    n g P r e � C M P d i e l e c t r i c l e v e l Figure 1.2: Definition of dishing and erosion

  • Electrical recommendations and formulas for metal fill in radio-frequency integrated circuits

    Creator:
    Gaskill, Steven
    Abstract:
    With increasing transistor operating frequencies, interconnects and passive devices are becoming performance limiters in integrated circuit (IC) designs. To combat this, the interconnect layers above the active silicon are trending toward low-κ dielectrics and Cu metallization. The use of these new materials has popularized chemical mechanical polishing (CMP) to planarize...
    Resource Type:
    Masters Thesis