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  • A digital multiplying delay locked loop for high frequency clock generation

    Creator:
    Uttarwar, Tushar
    Abstract:
    As Moore’s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks in such scaled processes is becoming a tough challenge. Digital phase locked loops (DPLLs) are being explored as an alternative to conventional analog PLLs but...
    Resource Type:
    Masters Thesis

  • Feedforward noise cancellation techniques

    Creator:
    Yang, Bangda
    Abstract:
    Supply noise is one of the major considerations in almost all analog building blocks. In the past, adequate supply rejection is usually achieved with circuit isolation or excess capacitive coupling. However, this brute force method requires large silicon area and degrades feedback bandwidth. In this study, a method of enhancing...
    Resource Type:
    Masters Thesis