Search Constraints

Start Over
Filtering by: Creator Kamvar, Z. N. Remove constraint Creator: Kamvar, Z. N. Contributor advisor sim Moon, Un-Ku Remove constraint Contributor advisor sim: Moon, Un-Ku Degree Level Master's Remove constraint Degree Level: Master's

Search Results

  • Design techniques for radiation hardened-phase locked loops

    Creator:
    Nemmani, Anantha Nag
    Abstract:
    Spacecrafts experience radiation in the course of their operation and all electronic equipment on board these spacecrafts has to be designed to withstand the effects of this radiation. This thesis describes the effects of total ionization dose (TID) and single event transients (SET) in phase-locked loops - an important circuit...
    Resource Type:
    Masters Thesis
    Full Text:
    blocks is explained in the following section. CTRLPFD + TDC N LF(z) Digital Loop Filter DCAO

  • High-speed switched-capacitor filters based on unity-gain buffers

    Creator:
    Bruneau, David
    Abstract:
    In this work a new voltage buffer, the drain-follower, achieves 300MHz band-width with 2pF load, a dc gain of 0.993V/V, 1mV offset voltage, -60 dB total harmonic distortion at 1.4Vpp output voltage and 6.5mW power dissipation from 5V supply. A unity-gain buffer switched-capacitor biquad filter has been implemented in 0.5μm...
    Resource Type:
    Masters Thesis
    Full Text:
    Improvement ................... 9 2.3 The PMOS source-follower with N-Well Buffer ....................... 11

  • An efficient switched capacitor buck-boost voltage regulator using delta-sigma control loop

    Creator:
    Rao, Arun
    Abstract:
    Voltage converters or charge pumps find their use in many circuits. They are extensively used in hand held devices as cell phones, pagers, PDA's and laptops. Some of the important issues relating to design of voltage regulators for handheld devices are size, efficiency and noise. Another important factor to be...
    Resource Type:
    Masters Thesis
    Full Text:
    possible gain settings 3 bits are e(n) 1 u(n) >® > H(z) > > y(n) x(n) Figure 5.1. Linear model of a L

  • A continuous time frequency translating delta Sigma Modulator

    Creator:
    Pulincherry, Anurag
    Abstract:
    This thesis presents a continuous time bandpass delta sigma modulator with frequency translation inside the delta sigma loop. The input IF signal is down converted to baseband after amplification by a low Q, wideband bandpass resonator. The down converted IF signal is digitized by a continuous time, second order lowpass...
    Resource Type:
    Masters Thesis
    Full Text:
    ................................................................................................ 28 4.4. Power pf v[n]-v[n-] vs quantiztion noise power

  • OP-AMP free SC biquad LPF and delta-sigma ADC

    Creator:
    Yoo, Kiseok
    Abstract:
    The objective of this work is to explore the feasibility of replacing conventional op-amps with inverters in switched-capacitor (SC) circuits. In order to verify the idea, a low-pass filter (LPF) and a second-order delta-sigma (∆Σ) analog-todigital converter (ADC) are designed in the 0.5-m CMOS technology. The low-pass filter structure is...
    Resource Type:
    Masters Thesis
    Full Text:
    . Two cascaded integrators are needed to implement a second- H(z) x(n) e(n) y(n) u(n) ― 21

  • Fast opamp-free delta sigma modulator

    Creator:
    Thomas, Daniel E.
    Abstract:
    Switched-capacitor (SC) circuits are commonly used for analog signal processing because they can be used to realize precision filters and data converters on an integrated circuit (IC). However, for high speed applications SC circuit operating speeds are limited by the internally-compensated opamps found in SC integrators, a common building block...
    Resource Type:
    Masters Thesis
    Full Text:
    simulation results for the z>I modulator........................................................ 44 5.5 Real

  • Generalized radix design techniques for low-power, low voltage pipelined and cyclic analog-digital converters

    Creator:
    Sharma, Vivek
    Abstract:
    This thesis proposes a novel technique for the design of pipelined and cyclic ADCs utilizing generalized radix gain stages. Several models have been proposed for the optimization of high performance pipelined ADCs by various researchers. This work builds upon them, using a simple but accurate model to estimate the optimal...
    Resource Type:
    Masters Thesis
    Full Text:
    be required to satisfy the Nyquist sampling criterion. )1( 1 2.)()( −− = �⋅= k N i

  • Oscillators and phase locked loops for space radiation environments

    Creator:
    Vandepas, Martin
    Abstract:
    Circuits operating outside the earth’s atmosphere are more vulnerable to cosmic radiation and require special design consideration. The purpose of this work is to explore methods of mitigating the effect of radiation in phase locked loop (PLL) circuits. Several voltage controlled oscillators (VCOs) and two complete PLLs are designed and...
    Resource Type:
    Masters Thesis
    Full Text:
    2.5 300 400 500 600 700 800 900 1000 1100 1200 Control Voltage (V) Fr eq ue n cy (M H z

  • Digital implementation of a mismatch-shaping successive-approximation ADC

    Creator:
    Coe, Matthew T.
    Abstract:
    Utilizing a two-capacitor topology, the digital implementation of an audio-band successive-approximation analog-to-digital converter (ADC) is explored in the context of mismatch-shaping where the mismatch estimates are accurate to the first order. A second-order Δ∑ loop was found to be effective in system simulations given a 0.1% capacitor mismatch. Spectral analysis...
    Resource Type:
    Masters Thesis
    Full Text:
    3.2 Flow graph for an N-bit charge-redistribution successive-approximation ADC

  • A 10 bit algorithmic A/D converter for a biosensor

    Creator:
    Rengachari, Thirumalai
    Abstract:
    This thesis presents a novel algorithmic A/D converter to be used in a biosensor. The converter is capable of a conversion rate of 1.5 bits/phase and hence the required conversion time is reduced. The proposed architecture is analyzed for non-ideal effects and compared with existing algorithmic A/D architectures. The converter...
    Resource Type:
    Masters Thesis
    Full Text:
    of 1-Bit/Phase............................................................. 29 5.2 N(N>1)-Bit/phase