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Filtering by: Creator Chen, Kuei-Lin Remove constraint Creator: Chen, Kuei-Lin Contributor advisor sim Moon, Un-Ku Remove constraint Contributor advisor sim: Moon, Un-Ku File Format application/pdf Remove constraint File Format: application/pdf

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  • Design techniques for PVT tolerant phase-locked loops

    Creator:
    Wu, Ting
    Abstract:
    The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
    Resource Type:
    Dissertation
    Full Text:
    Vandepas, Charlie Myers, Dr. Zhenyong Zhang, Dr. Qingdong Meng, Xuefeng Chen, Dr. Ruopeng Wang, Won-Seok