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Filtering by: Subject Integrated passive components -- Design and construction Committee Member Eugene, Zhang

Low power scheduling schemes that consider latency and resource constraints at multiple voltages

Creator:

Huang, Shyh-Sen

Abstract:

Power reduction can be achieved at many different levels, such as architecture, algorithm, logic, and transistor levels in circuit design. This thesis focuses on low power scheduling at the algorithm level. We present a latency-constrained scheduling and a latency and resource constrained scheduling, which minimize power consumption for the resources...

Resource Type:

Masters Thesis

Full Text:

FIGURES Figure Page 1. Design Flow and the Levels of Abstraction