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Filtering by: Subject Integrated circuits -- Very large scale integration -- Design and construction -- Mathematical models Remove constraint Subject: Integrated circuits -- Very large scale integration -- Design and construction -- Mathematical models Committee Member Hackleman, David Remove constraint Committee Member: Hackleman, David

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  • Low-complexity high-speed VLSI design of low-density parity-check decoders

    Creator:
    Cui, Zhiqiang
    Abstract:
    Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g.,...
    Resource Type:
    Dissertation
    Full Text:
    considers various VLSI design issues of LDPC decoder and develops efficient approaches for reducing memory