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Filtering by: Creator Hansen, E. M. Remove constraint Creator: Hansen, E. M. Committee Member Liu, Huaping Remove constraint Committee Member: Liu, Huaping Committee Member Bose, Bella Remove constraint Committee Member: Bose, Bella

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  • Variable sampling compensation of networked control systems with delays using neural networks

    Creator:
    Lopez-Echevarria, Daniel
    Abstract:
    In networked control systems (NCS) information or packets usually flow from a sensor or a set of sensors to a remotely located controller. Then the controller processes the received information and sends a series of control commands to the actuators through a communication network which could be either wireless or...
    Resource Type:
    Dissertation
    Full Text:
    Networks. Abstract approved: Mario E. Magaña In networked control systems (NCS) information or packets

  • Adaptive Streaming Methods using Dual Protocols and Reinforcement Learning

    Creator:
    Gatimu, Kevin
    Abstract:
    The ubiquity of high quality video and proliferation of mobile devices has contributed to an unprecedented rise in video consumption. HTTP, in conjunction with adaptive streaming, has become the de facto mechanism for delivering the vast majority of video as it readily caters to heterogeneous networks and devices. This dissertation...
    Resource Type:
    Dissertation
    Full Text:
    an M/D/1/K Queue . . 105 7.3.4 The qMDP State Space

  • Coordinating secondary-user behaviors for inelastic traffic reward maximization in large-scale DSA networks

    Creator:
    NoroozOliaee, MohammadJavad
    Abstract:
    We develop efficient coordination techniques that support inelastic traffic in large-scale distributed dynamic spectrum access DSA networks. By means of any learning algorithm, the proposed techniques enable DSA users to locate and exploit spectrum opportunities effectively, thereby increasing their achieved throughput (or "rewards" to be more general). Basically, learning algorithms...
    Resource Type:
    Masters Thesis
    Full Text:
    has the remaining c+ k agents (sin e n− c(m− 1) = c+ k). We pro eed with the proof by omparing C

  • Low-complexity high-speed VLSI design of low-density parity-check decoders

    Creator:
    Cui, Zhiqiang
    Abstract:
    Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g.,...
    Resource Type:
    Dissertation
    Full Text:
    binary (n, k) LDPC code specified by a parity-check matrix H with M rows and N columns. Using a

  • Information theoretic approach to quantization and classification for signal processing, communications, and machine learning applications

    Creator:
    Thuan Nguyen D.
    Abstract:
    There are five main contributions of this dissertation. The first contribution is new closed-form expressions for channel capacity of a new class of channel matrices. The second contribution is the discovery of the structure for optimal binary quantizer and the associated methods for finding an optimal quantizer that maximizes mutual...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . 131 6.4 (a) S(emax) as a function of emax; (b) Nmin = 2S(e max) as a function of emax. . . . 131 6.5

  • Low-power dynamic CMOS circuits in high-performance memory arrays

    Creator:
    Patwary, Md. Ataur R.
    Abstract:
    Dynamic CMOS circuits are commonly used in high-performance memory arrays to implement wide-NOR logic functions for their read and search operations. This is because dynamic circuits have significantly higher speed and lower area compared to static circuits for performing similar operations. Register File (RF) arrays are located at the top...
    Resource Type:
    Dissertation
    Full Text:
    M x 2 N bits of data is shown in Figure 1.10. The read/write decoders convert N-bit read/write