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Filtering by: Alternative title ssim Technical note no. D-11 Remove constraint Alternative title ssim: Technical note no. D-11 Committee Member Liu, Huaping Remove constraint Committee Member: Liu, Huaping Degree Name Master of Science (M.S.) Remove constraint Degree Name: Master of Science (M.S.)

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  • An ultra low voltage micropower GPS receiver RF front-end for wildlife tracking

    Creator:
    Heiberg, Adam C.
    Abstract:
    A fully integrated CMOS GPS receiver RF front end optimized for low power operation is presented. The system operates with a supply voltage down to 250 mV. A prototype has been fabricated in a 0.13μm CMOS process and includes a low voltage LNA, quadrature oscillators, and quadrature mixers. It exhibits...
    Resource Type:
    Masters Thesis
    Full Text:
    this work. The LNA is integrated on chip, eliminating the 11 need for an active antenna. Note that

  • Opportunistic bandwidth sharing through reinforcement learning

    Creator:
    Venkatraman, Pavithra
    Abstract:
    The enormous success of wireless technology has recently led to an explosive demand for, and hence a shortage of, bandwidth resources. This expected shortage problem is reported to be primarily due to the inefficient, static nature of current spectrum allocation methods. As an initial step towards solving this shortage problem,...
    Resource Type:
    Masters Thesis
    Full Text:
    at the current time step; i.e., no PUs are currently using band bi. Note that state s0 corresponds

  • Analysis and modeling of coplanar on-chip interconnects on silicon substrates

    Creator:
    Luoh, Yi
    Abstract:
    The electrical behavior of on-chip interconnects has become a dominant factor in silicon-based high speed, RF, and mixed-signal integrated circuits. In particular, the frequency-dependent loss mechanisms in heavily-doped silicon substrates can have a large influence on the transmission characteristics of on-chip interconnects. To optimize the performance of the integrated circuit,...
    Resource Type:
    Masters Thesis
    Full Text:
    on-chip interconnect configurations: (a) microstrip, (b) copla- nar strip, (c) coplanar waveguide, (d

  • A 5 GHz Wi-Fi Receiver Front End with 4x80 MHz Channels for a High Accuracy Indoor Localization System

    Creator:
    Gray, Kyle L.
    Abstract:
    The ability to accurately locate people and objects indoors will enable opportunities for control and automation of indoor environments. Current indoor localization solutions require dedicated hardware which must be custom tailored to each application. There are large technological, societal, and economic benefits in developing a more general purpose system that...
    Resource Type:
    Masters Thesis
    Full Text:
    , Author ACKNOWLEDGMENTS There are no endeavors in life that are accomplished individually and this

  • Architecture design of multiplexed incremental analog-to-digital converters

    Creator:
    Zhang, Zhiqing
    Abstract:
    Analog-to-Digital Data Converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental data converters (IDCs) provide a solution for such measurement applications. Since IDCs are essentially delta-sigma converters with reset operation before each conversion, they retain most of the advantages...
    Resource Type:
    Masters Thesis
    Full Text:
    Steensgaard, Wenhuan Yu and Attila Sarhegyi for all the useful technical discussions during the research

  • Noise optimization for low-voltage CMOS audio preamplifier systems

    Creator:
    Brown, Matthew Eugene
    Abstract:
    There is a large and growing market for portable consumer audio products with very small size. As the size of these products is reduced, the area occupied by batteries becomes significant and hence limits the number of batteries to one. In order to build such small products, high levels of...
    Resource Type:
    Masters Thesis
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6 Device Operating Regions

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    technique of dynamically steering instructions requires slightly more logic to implement, but incurs no

  • Dual referencing guidelines to minimize power delivery noise coupling

    Creator:
    Mark, Shannon
    Abstract:
    Dual referencing has been garnering a lot of attention in the power integrity community, specifically in the voltage mode driver application because it shows a lower overall power delivery noise (PDN) compared to other signal referencing types. Additionally, the increasing push to drive down package and board manufacturing costs is...
    Resource Type:
    Masters Thesis
    Full Text:
    rails can no longer be neglected. This work provides a comprehensive study of PDN coupling onto

  • Understanding the ultra-wideband channel within a computer chassis

    Creator:
    Redfield, Stephen J.
    Abstract:
    Recent developments in computing technology have generated a demand for more streamlined and effective test systems. By replacing traditional in-chassis wired interconnects with a broadcast wireless system, fault detection and error susceptibility will drastically improve, input/output capabilities will expand, and routing complexity will decrease. Ultra-wideband impulse radio's (UWB-IR) characteristic multipath-immunity...
    Resource Type:
    Masters Thesis
    Full Text:
    simplified to (2.2) 11 for the path loss L(d). L(d) = ( c 4πdf )2 ( 1 d )n (2.2) Since the channel

  • Generalized radix design techniques for low-power, low voltage pipelined and cyclic analog-digital converters

    Creator:
    Sharma, Vivek
    Abstract:
    This thesis proposes a novel technique for the design of pipelined and cyclic ADCs utilizing generalized radix gain stages. Several models have been proposed for the optimization of high performance pipelined ADCs by various researchers. This work builds upon them, using a simple but accurate model to estimate the optimal...
    Resource Type:
    Masters Thesis
    Full Text:
    the course of my work. Not only have I gained from his vast technical experience, but also he has