Index Catalog // Hyrax

A survey on continuous-time modulators : theory, designs and implementations

Schöpfer:: Gao, Xiaoran
Abstract:: Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy...
Resource Type:: Masters Thesis

Architecture design of multiplexed incremental analog-to-digital converters

Schöpfer:: Zhang, Zhiqing
Abstract:: Analog-to-Digital Data Converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental data converters (IDCs) provide a solution for such measurement applications. Since IDCs are essentially delta-sigma converters with reset operation before each conversion, they retain most of the advantages...
Resource Type:: Masters Thesis

Modified VLSI designs for error correction codes

Schöpfer:: Chen, Lupin
Abstract:: Nowadays, error correction codes have become an integral part in almost all the modern digital communication and storage systems. With the continuously increasing demands for higher speed and lower power communication systems, efficient VLSI implementations of those error correction codes have great importance for practical applications. In this thesis, several...
Resource Type:: Masters Thesis

Comparison and impact of substrate noise due to clocked and clockless circuitry

Schöpfer:: Le, Jim K.
Abstract:: Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention Logic (NCL) and traditional Clocked Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
Resource Type:: Masters Thesis

Single-level dynamic register caching architecture for high-performance superscalar processors

Schöpfer:: Liebert, John A.
Abstract:: The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
Resource Type:: Masters Thesis

Scaled modeling and simulation of ocean wave linear generator buoy systems

Schöpfer:: Gore, Ganesh P.
Abstract:: Accurate scaled modeling and simulation are critical to advancing ocean wave linear generator buoys. A 100th scaled model of ocean wave generator buoy systems is analyzed by solving the Navier-Stokes equations. These equations are numerically solved using Computational Fluid Dynamics (CFD) by implementing the front capturing method. In this thesis,...
Resource Type:: Masters Thesis

A channelized digital receiver design for UWB sytems in a multipath indoor environment

Schöpfer:: Chang, Yuhao
Abstract:: This thesis presents a channelized digital receiver design for UWB sytems in a multipath indoor environment. The UWB technology has been used for commercial and military purposes due to a number of advantages such as low-power consumption, noise-like and carrier free. The energy of UWB signal is spread over a...
Resource Type:: Masters Thesis

Noise optimization for low-voltage CMOS audio preamplifier systems

Schöpfer:: Brown, Matthew Eugene
Abstract:: There is a large and growing market for portable consumer audio products with very small size. As the size of these products is reduced, the area occupied by batteries becomes significant and hence limits the number of batteries to one. In order to build such small products, high levels of...
Resource Type:: Masters Thesis

A comparative study of lowpass continuous-time delta-sigma modulators with pulse-shaped DACs

Schöpfer:: Fang, Jie
Abstract:: Recently, continuous-time ΔΣ modulators are appearing increasingly often in both the literature and the marketplace due to their features of inherent antialiasing and relaxed requirements for opamp and so on. However, several nonideal factors such as clock jitter, excess loop delay, inter-symbol interference and so on, degrade the SNR performance...
Resource Type:: Masters Thesis

Hyrax

A survey on continuous-time modulators : theory, designs and implementations

Architecture design of multiplexed incremental analog-to-digital converters

Modified VLSI designs for error correction codes

Comparison and impact of substrate noise due to clocked and clockless circuitry

Single-level dynamic register caching architecture for high-performance superscalar processors

Scaled modeling and simulation of ocean wave linear generator buoy systems

A channelized digital receiver design for UWB sytems in a multipath indoor environment

Noise optimization for low-voltage CMOS audio preamplifier systems

A comparative study of lowpass continuous-time delta-sigma modulators with pulse-shaped DACs

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