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Filtering by: Creator Tran, Jenny K. Remove constraint Creator: Tran, Jenny K. Committee Member Liu, Huaping Remove constraint Committee Member: Liu, Huaping Subject Phase-locked loops Remove constraint Subject: Phase-locked loops

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  • High-speed CMOS dual-modulus presalers for frequency synthesis

    Creator:
    Desikachari, Ranganathan
    Abstract:
    Phase-locked loop (PLL) frequency synthesizers lie at the heart of most radio transceivers. An important objective of the electronics and communications industry is to design high-speed building blocks which dissipate the lowest possible power, and to ac- complish this with the cheapest technology. The dual-modulus prescaler is one of the...
    Resource Type:
    Masters Thesis
    Full Text:
    - Pass Filter VCO X(t) Y(t) (a) G LPF (s) X(s) Y(s) K PD K vco s (b

  • Semi-digital PLL architecture for ultra low bandwidth applications

    Creator:
    George, Edmond
    Abstract:
    Phase Locked Loops(PLLs) are an integral part of almost every electronic system. Systems involving low frequency clocks often require PLLs with low bandwidth. The area occupied by the large loop filter capacitor and resistor in a low bandwidth PLL design makes the realization of traditional charge-pump PLL architecture impractical on...
    Resource Type:
    Masters Thesis
    Full Text:
    is below the target frequency of 20kHz. Tran- 31 sistor N7 is driven by the output of the charge