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Filtering by: Subject Electronic circuits -- Noise Remove constraint Subject: Electronic circuits -- Noise Committee Member Liu, Huaping Remove constraint Committee Member: Liu, Huaping

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  • Noise optimization for low-voltage CMOS audio preamplifier systems

    Creator:
    Brown, Matthew Eugene
    Abstract:
    There is a large and growing market for portable consumer audio products with very small size. As the size of these products is reduced, the area occupied by batteries becomes significant and hence limits the number of batteries to one. In order to build such small products, high levels of...
    Resource Type:
    Masters Thesis
    Full Text:
    this document which will focus on the noise inherent in the circuit devices. 4.2. Zipper Noise

  • An enhanced swing differential Colpitts CMOS VCO for low-voltage operation

    Creator:
    Farahbakhshian, Farhad
    Abstract:
    An enhanced swing differential Colpitts VCO (ESDC-VCO) dramatically improves the swing of a Colpitts VCO by allowing the signal to swing below ground and above the supply voltage. Fabricated in a 1P8M 0.13 um CMOS process, the ESDC-VCO operates at 4.9GHz with a 0.475-V supply and consumes 2.7mW. The measured...
    Resource Type:
    Masters Thesis
    Full Text:
    and consumes 2.7mW. The measured phase noise is -136.2 dBc/Hz at a 3-MHz frequency offset. The ESDC

  • Comparison and impact of substrate noise due to clocked and clockless circuitry

    Creator:
    Le, Jim K.
    Abstract:
    Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention Logic (NCL) and traditional Clocked Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
    Resource Type:
    Masters Thesis
    Full Text:
    larger scale digital circuit, the substrate noise improvement offered by an asynchronous 8051 processor

  • Low noise clocking for high speed serial links

    Creator:
    Brownlee, Merrick
    Abstract:
    As the functionality of digital chips continues to increase dramatically, chip- to-chip communication bandwidths must scale accordingly to avoid constraining the overall system performance. Therefore, high speed transceiver design has be- come an important research topic. In particular, the performance of the circuits that are responsible for timing accuracy are...
    Resource Type:
    Dissertation
    Full Text:
    effectiveness of a circuit or the severity of a noise source by examining before and after eye diagrams. Total

  • A dual-path 2-0 MASH ADC with dual digital error correction

    Creator:
    Zhang, Zhenyong
    Abstract:
    This dissertation presents a dual-path 2-0 MASH (Multi-stAge-noise -SHaping) ADC with two verified digital corrections of DAC mismatch error and quantization noise leakage. By using these two techniques, the requirements for the analog circuits are greatly relaxed. The dual-path structure generates two outputs, one only composed of conversion errors, the...
    Resource Type:
    Dissertation
    Full Text:
    ………………………………………………………...37 4.2 Noise analysis……………………………………………………………..41 Chapter 5 Prototype chip design---circuit and

  • Pattern discovery in noisy images

    Creator:
    Dhamodaran, Sharath Kumar
    Abstract:
    The Focused Ion Beam (FIB) tool is a versatile instrument for nano-machining in circuit editing. Circuit editing is one of the most important steps in the design of an electronic circuit on a chip. Circuit editing can be improved by imaging of silicon plates and analyzing the resultant images. However...
    Resource Type:
    Masters Thesis

  • Noise and Blocker Cancellation Techniques for Power and Area Efficient Wireless Receivers

    Creator:
    Pourbagheri, Saeed
    Abstract:
    The design of mobile wireless devices has always focused on reducing power, area, and cost. This dissertation proposes two techniques that are leveraged to save power and area and therefore cost. The first techniques reduces the noise in the receiver and results in a relaxed power requirement. The second technique...
    Resource Type:
    Dissertation
    Full Text:
    . Due to the large gain in the previous amplifying stage, noise generated in the multiplier circuit is

  • Ultra low capacitance RFIC probe

    Creator:
    Jacob, Michael E.
    Abstract:
    In Radio Frequency Integrated Circuits (RFIC) or high frequency digital ICs, there is a demand to probe the internal nodes for testing. The ultra low capacitance RFIC probe presented in his work is a flexible tool for these applications. The probe utilizes the coupling between a tungsten needle and the...
    Resource Type:
    Masters Thesis
    Full Text:
    low capacitance of the probe enables low probe loading on the circuit under test. With capacitive

  • High-speed CMOS dual-modulus presalers for frequency synthesis

    Creator:
    Desikachari, Ranganathan
    Abstract:
    Phase-locked loop (PLL) frequency synthesizers lie at the heart of most radio transceivers. An important objective of the electronics and communications industry is to design high-speed building blocks which dissipate the lowest possible power, and to ac- complish this with the cheapest technology. The dual-modulus prescaler is one of the...
    Resource Type:
    Masters Thesis
    Full Text:
    the power con- sumed to 2.5 mW. The circuit was implemented in a 0.25µm National BiCMOS process

  • Modified VLSI designs for error correction codes

    Creator:
    Chen, Lupin
    Abstract:
    Nowadays, error correction codes have become an integral part in almost all the modern digital communication and storage systems. With the continuously increasing demands for higher speed and lower power communication systems, efficient VLSI implementations of those error correction codes have great importance for practical applications. In this thesis, several...
    Resource Type:
    Masters Thesis
    Full Text:
    reduce the average number of decoding iterations in the low to medium signal to noise ratio (SNR) range