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Filtering by: Creator Church, John A. Remove constraint Creator: Church, John A. Committee Member Liu, Huaping Remove constraint Committee Member: Liu, Huaping

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  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    12, 2015. Title: The Architecture of a Reusable Built-In Self-Test for Link Training, IO and

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF John A. Liebert for the degree of Master of Science in Electrical

  • Side channel attack resistant elliptic curves cryptosystem on multi-cores for power efficiency

    Creator:
    Yoo, Jaewon
    Abstract:
    The Advent of multi-cores allows programs to be executed much faster than before. Cryptoalgorithms use long-bit words thus parallelizing these operations on multi-cores will achieve significant performance improvement. However, not all long-bit word operations in cryptosystems are suitable for parallel execution on multi-cores. In particular, long-bit words used in Elliptic...
    Resource Type:
    Masters Thesis
    Full Text:
    appreciation to Professor Huaiping Liu, Traylor Roger, and John A. Nairn for their serving in my graduate

  • A novel linear generator for wave energy applications

    Creator:
    Ernst, Steven George
    Abstract:
    With the increasing effort to identify alternative methods of energy generation, extraction of ocean energy has gathered a large interest. Research and industry have begun considering wave energy as the next new alternative energy. The unique challenges of ocean energy requires a wave energy converter to be both robust and...
    Resource Type:
    Masters Thesis
    Full Text:
    , 2009. Title: A Novel Linear Generator for Wave Energy Applications Abstract approved: Ted K. Brekken

  • Modeling and analysis of spur structure of digital-to-time conversion based frequency synthesizers

    Creator:
    Talwalkar, Sumit A.
    Abstract:
    Frequency synthesizers are critical components of all communication systems. This thesis considers the issue of undesirable frequency spurs of a relatively recent type of frequency synthesis architecture called digital-to-time conversion (DTC). The DTC-based frequency synthesis architecture has important performance benefits over older frequency synthesizers, such as fast frequency switching, large...
    Resource Type:
    Dissertation
    Full Text:
    ______________________________________________________ AN ABSTRACT OF THE THESIS OF Sumit A. Talwalkar for the degree of Doctor of

  • Model development via delay extraction for the time-domain simulation of lossy transmission lines.

    Creator:
    Blevins, Chris
    Abstract:
    This thesis presents two new approaches for the broadband, time-domain modeling of lossy transmission lines. Each approach is based on an alternative derivation of delay extraction in order to separate the line's linear phase from its attenuation and dispersion. Augmentation networks represent the derived attenuation networks as rational function approximations....
    Resource Type:
    Masters Thesis
    Full Text:
    implemented in a SPICE circuit simulator for transient analysis. The first approach to extract delay is

  • Low-power high-resolution delta-sigma ADC design techniques

    Creator:
    Wang, Tao
    Abstract:
    This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the...
    Resource Type:
    Dissertation
    Full Text:
    Gabor C. Temes This dissertation presents a low-power high-resolution delta-sigma ADC. Two

  • Analysis and design on low-power multi-Gb/s serial links

    Creator:
    Hu, Kangmin
    Abstract:
    High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most...
    Resource Type:
    Dissertation
    Full Text:
    this work, a system level statistical analysis of serial links is first described, and compares the

  • Surface-Normal Modulation of Fano Resonances in Metallic Photonic Crystals for Free-Space Optical Interconnects

    Creator:
    Ren, Fanghui
    Abstract:
    This dissertation focuses on the development of ultra-compact optical devices for free-space modulation. We propose a surface-normal modulator using metallic photonic crystals for free-space optical interconnects. The active control of light intensity is achieved by engineering the Fano resonances in metallic photonic crystals. Both thermo-optic modulation and electro-optic modulation of...
    Resource Type:
    Dissertation
    Full Text:
    devices for free-space modulation. We propose a surface-normal modulator using metallic photonic

  • Some contributions to asymmetric error control codes

    Creator:
    Elmougy, Samir
    Abstract:
    In some practical systems, most of the errors are of 1 → 0 type and 0 → 1 errors occur very rarely. In this thesis, first, the capacity of the asymmetric channel is derived. The capacity of the binary symmetric channel (BSC) and the Z-channel can be derived from this...
    Resource Type:
    Dissertation
    Full Text:
    beyond the max- imum designed error detection capability are described. Third, a new class of a