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Filtering by: Creator Downs, Leslie E. Remove constraint Creator: Downs, Leslie E. Committee Member Liu, Huaping Remove constraint Committee Member: Liu, Huaping

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  • Novel power conditioning circuits for piezoelectric micro power generators

    Creator:
    Han, Jifeng
    Abstract:
    Advanced low power devices promote the development of micro power generators (MPGs) to replace the batteries to power them. Due to the trend in decreasing integrated circuit (IC) supply voltages, power supply designers are facing more and more serious challenges. The objective of this research is to design a power...
    Resource Type:
    Dissertation
    Full Text:
    synchronous rectification technique. The dc-dc regulator is a charge pump-based step-down converter

  • An ultra low voltage micropower GPS receiver RF front-end for wildlife tracking

    Creator:
    Heiberg, Adam C.
    Abstract:
    A fully integrated CMOS GPS receiver RF front end optimized for low power operation is presented. The system operates with a supply voltage down to 250 mV. A prototype has been fabricated in a 0.13μm CMOS process and includes a low voltage LNA, quadrature oscillators, and quadrature mixers. It exhibits...
    Resource Type:
    Masters Thesis
    Full Text:
    op- eration is presented. The system operates with a supply voltage down to 250 mV. A prototype has

  • Low-power design techniques for low-voltage analog-to-digital converters

    Creator:
    Kim, Min Gyu
    Abstract:
    The demand for portable electronic systems and the continued down-scaling of device dimensions resulted in rapid improvement in the performance of integrated systems. Several low-voltage design techniques have been proposed to operate analog circuits with sub-1V supply. However, these techniques require higher power consumption to achieve large dynamic range while...
    Resource Type:
    Dissertation
    Full Text:
    demand for portable electronic systems and the continued down-scaling of device dimensions resulted in

  • Low-voltage data converters

    Creator:
    Meng, Qingdong
    Abstract:
    With the growing demand for portable/consumer electronics, such as digital audio/video (AV), the downscaling of device dimensions, which enables the integration of an increasing number of transistors in a single chip, is mandatory. This trend also continuously pushes the power supply voltage down to reduce the power consumption and improve...
    Resource Type:
    Dissertation
    Full Text:
    supply voltage down to reduce the power consumption and improve the reliability of gate dielectrics

  • Dual referencing guidelines to minimize power delivery noise coupling

    Creator:
    Mark, Shannon
    Abstract:
    Dual referencing has been garnering a lot of attention in the power integrity community, specifically in the voltage mode driver application because it shows a lower overall power delivery noise (PDN) compared to other signal referencing types. Additionally, the increasing push to drive down package and board manufacturing costs is...
    Resource Type:
    Masters Thesis
    Full Text:
    drive down package and board manufacturing costs is another essential factor to consider dual

  • Modeling and analysis of spur structure of digital-to-time conversion based frequency synthesizers

    Creator:
    Talwalkar, Sumit A.
    Abstract:
    Frequency synthesizers are critical components of all communication systems. This thesis considers the issue of undesirable frequency spurs of a relatively recent type of frequency synthesis architecture called digital-to-time conversion (DTC). The DTC-based frequency synthesis architecture has important performance benefits over older frequency synthesizers, such as fast frequency switching, large...
    Resource Type:
    Dissertation
    Full Text:
    -down weak desirable signal. Unlike harmonic spurs that are known to be at multiples of the carrier

  • Adaptive, wideband analog-to-digital conversion for convergent communication systems

    Creator:
    Batten, Robert D., 1973-
    Abstract:
    The exponential rate of advances in modern communication devices in the last several years have brought us higher levels of functionality and performance as well as reductions in physical size and power consumption. To continue this rate of advancement, next generation systems require wider bandwidth and higher resolution ADCs. Additionally,...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . 42 3.2 A Leslie-Singh∆Σ modulator. . . . . . . . . . . . . . . . . . . . . . . 44 LIST OF FIGURES

  • Low-power dynamic CMOS circuits in high-performance memory arrays

    Creator:
    Patwary, Md. Ataur R.
    Abstract:
    Dynamic CMOS circuits are commonly used in high-performance memory arrays to implement wide-NOR logic functions for their read and search operations. This is because dynamic circuits have significantly higher speed and lower area compared to static circuits for performing similar operations. Register File (RF) arrays are located at the top...
    Resource Type:
    Dissertation
    Full Text:
    2.4. Option 2 – Bit-line Organization of an RF with 8 pull-downs/LBL and using GBL NAND gate

  • Coordinating secondary-user behaviors for inelastic traffic reward maximization in large-scale DSA networks

    Creator:
    NoroozOliaee, MohammadJavad
    Abstract:
    We develop efficient coordination techniques that support inelastic traffic in large-scale distributed dynamic spectrum access DSA networks. By means of any learning algorithm, the proposed techniques enable DSA users to locate and exploit spectrum opportunities effectively, thereby increasing their achieved throughput (or "rewards" to be more general). Basically, learning algorithms...
    Resource Type:
    Masters Thesis
    Full Text:
    NoroozOliaee for the degree of Master of S ien e in Computer S ien e presented on Mar h 6 , 2013. Title

  • Design techniques for low-power multi-GS/s analog-to-digital converters

    Creator:
    Jiang, Tao
    Abstract:
    Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off...
    Resource Type:
    Dissertation
    Full Text:
    Motivation 1.1. As CMOS technology scales down to the magnitude of nanometer, digital signal processing