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Filtering by: Creator Durkee, P. A. Remove constraint Creator: Durkee, P. A. Committee Member Liu, Huaping Remove constraint Committee Member: Liu, Huaping

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  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    , longer wires have scaled at a slower rate and in some cases have grown larger as chip size and

  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    : Adjacent neighborhood of a memory cell B (source P. de Jong and A. J. van de Goor [12]) Different

  • Information theoretic approach to quantization and classification for signal processing, communications, and machine learning applications

    Creator:
    Thuan Nguyen D.
    Abstract:
    There are five main contributions of this dissertation. The first contribution is new closed-form expressions for channel capacity of a new class of channel matrices. The second contribution is the discovery of the structure for optimal binary quantizer and the associated methods for finding an optimal quantizer that maximizes mutual...
    Resource Type:
    Dissertation
    Full Text:
    that when the ratio of the channel conditional density r(y) = P (Y=y|X=0)P (Y=y|X=1) is a strictly

  • Scaled modeling and simulation of ocean wave linear generator buoy systems

    Creator:
    Gore, Ganesh P.
    Abstract:
    Accurate scaled modeling and simulation are critical to advancing ocean wave linear generator buoys. A 100th scaled model of ocean wave generator buoy systems is analyzed by solving the Navier-Stokes equations. These equations are numerically solved using Computational Fluid Dynamics (CFD) by implementing the front capturing method. In this thesis,...
    Resource Type:
    Masters Thesis
    Full Text:
    linear generator buoys. A 100th scaled model of ocean wave generator buoy systems is analyzed by

  • A novel linear generator for wave energy applications

    Creator:
    Ernst, Steven George
    Abstract:
    With the increasing effort to identify alternative methods of energy generation, extraction of ocean energy has gathered a large interest. Research and industry have begun considering wave energy as the next new alternative energy. The unique challenges of ocean energy requires a wave energy converter to be both robust and...
    Resource Type:
    Masters Thesis
    Full Text:
    Magnet Thickness, h (in mm) R e a l P o w e r (W a tt s ) c=1mm c=2mm c=3mm c=4mm c

  • Methods for evaluating the impact of renewable resource variability on grid operation and planning

    Creator:
    Halamay, Douglas A.
    Abstract:
    With the recent interest in increasing the penetration of renewable energy sources onto the power grid, there has been an unprecedented rapid deployment of wind generation, especially in the US Pacific Northwest. While wind farm developers have continued to expand their operations, power system operators are left to deal with...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF Douglas A. Halamay for the degree of Master of Science in Electrical

  • Immune radio architecture for platform interference

    Creator:
    Alban, Eduardo
    Abstract:
    The decrease of switching times accompanied by the corresponding increase of clock speeds and data rates, contributes to improve the overall system computational performance. At the same time, they also affect wireless communications due to an increment in the emissions of electromagnetic radiation on the radio bands. In this dissertation...
    Resource Type:
    Dissertation
    Full Text:
    ) ) . (2.8) Figure 2.5 shows the power spectrum of a random signal with uneven transition times for p = 1/2

  • Variable sampling compensation of networked control systems with delays using neural networks

    Creator:
    Lopez-Echevarria, Daniel
    Abstract:
    In networked control systems (NCS) information or packets usually flow from a sensor or a set of sensors to a remotely located controller. Then the controller processes the received information and sends a series of control commands to the actuators through a communication network which could be either wireless or...
    Resource Type:
    Dissertation
    Full Text:
    represented in Fig. 2.5. The value of the signal ak is predicted on the basis of a linear combination of p

  • Modeling and analysis of spur structure of digital-to-time conversion based frequency synthesizers

    Creator:
    Talwalkar, Sumit A.
    Abstract:
    Frequency synthesizers are critical components of all communication systems. This thesis considers the issue of undesirable frequency spurs of a relatively recent type of frequency synthesis architecture called digital-to-time conversion (DTC). The DTC-based frequency synthesis architecture has important performance benefits over older frequency synthesizers, such as fast frequency switching, large...
    Resource Type:
    Dissertation
    Full Text:
    ______________________________________________________ AN ABSTRACT OF THE THESIS OF Sumit A. Talwalkar for the degree of Doctor of

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    ) without ports b 32 Data width of the architecture d --- Length of a wire (distance) p --- Total