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  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    versus a baseline NoC and ideal communi- cation. (a) Ideal communication; (b) Baseline NoC; and (c) SWIFT

  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    : Adjacent neighborhood of a memory cell B (source P. de Jong and A. J. van de Goor [12]) Different

  • A novel linear generator for wave energy applications

    Creator:
    Ernst, Steven George
    Abstract:
    With the increasing effort to identify alternative methods of energy generation, extraction of ocean energy has gathered a large interest. Research and industry have begun considering wave energy as the next new alternative energy. The unique challenges of ocean energy requires a wave energy converter to be both robust and...
    Resource Type:
    Masters Thesis
    Full Text:
    pressure is then converted to electrical energy. 6 (a) Point Absorber [10] (b) Attenuator [11] Figure

  • Methods for evaluating the impact of renewable resource variability on grid operation and planning

    Creator:
    Halamay, Douglas A.
    Abstract:
    With the recent interest in increasing the penetration of renewable energy sources onto the power grid, there has been an unprecedented rapid deployment of wind generation, especially in the US Pacific Northwest. While wind farm developers have continued to expand their operations, power system operators are left to deal with...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF Douglas A. Halamay for the degree of Master of Science in Electrical

  • Understanding the ultra-wideband channel within a computer chassis

    Creator:
    Redfield, Stephen J.
    Abstract:
    Recent developments in computing technology have generated a demand for more streamlined and effective test systems. By replacing traditional in-chassis wired interconnects with a broadcast wireless system, fault detection and error susceptibility will drastically improve, input/output capabilities will expand, and routing complexity will decrease. Ultra-wideband impulse radio's (UWB-IR) characteristic multipath-immunity...
    Resource Type:
    Masters Thesis
    Full Text:
    Understanding the Ultra-wideband Channel within a Computer Chassis by Stephen J. Redfield A THESIS submitted

  • Side channel attack resistant elliptic curves cryptosystem on multi-cores for power efficiency

    Creator:
    Yoo, Jaewon
    Abstract:
    The Advent of multi-cores allows programs to be executed much faster than before. Cryptoalgorithms use long-bit words thus parallelizing these operations on multi-cores will achieve significant performance improvement. However, not all long-bit word operations in cryptosystems are suitable for parallel execution on multi-cores. In particular, long-bit words used in Elliptic...
    Resource Type:
    Masters Thesis
    Full Text:
    P’3 P3 Addition P3 = P1 + P2 Doubling P3 = P1 + P1 GF(p)d, e a,b,c = 0;p>3;4d 3 +27e 2

  • Modeling and analysis of spur structure of digital-to-time conversion based frequency synthesizers

    Creator:
    Talwalkar, Sumit A.
    Abstract:
    Frequency synthesizers are critical components of all communication systems. This thesis considers the issue of undesirable frequency spurs of a relatively recent type of frequency synthesis architecture called digital-to-time conversion (DTC). The DTC-based frequency synthesis architecture has important performance benefits over older frequency synthesizers, such as fast frequency switching, large...
    Resource Type:
    Dissertation
    Full Text:
    operation in 65nm CMOS”, ISSCC, pp. 516 – 517 and 632, 2008. [1.9] J. Tierney, C. Rader, and B. Gold, “A

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    ) without ports b 32 Data width of the architecture d --- Length of a wire (distance) p --- Total

  • A multi-bit hybrid DSM over full-scale range without feedback DEM

    Creator:
    Kwon, Sunwoo, 1974-
    Abstract:
    Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a ∆Σ ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) ∆Σ Modulator (∆ΣM) is inadequate for low-power wideband applications...
    Resource Type:
    Dissertation
    Full Text:
    modulators: (a) SNDR versus bandwidth and (b) Power con- sumption versus bandwidth

  • Some contributions to asymmetric error control codes

    Creator:
    Elmougy, Samir
    Abstract:
    In some practical systems, most of the errors are of 1 → 0 type and 0 → 1 errors occur very rarely. In this thesis, first, the capacity of the asymmetric channel is derived. The capacity of the binary symmetric channel (BSC) and the Z-channel can be derived from this...
    Resource Type:
    Dissertation
    Full Text:
    ). Proof: Let S [(E e) (xh xCh)] (mod 4). If B = 4j + 1, j N, then the values for (E e) and (xC,, xCh) are