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  • Design Techniques of High-Speed Silicon Photonics Transceiver

    Creator:
    Li, Hao
    Abstract:
    The rapid scaling of network bandwidth and data center throughput has motivated the wide adoption of high speed transceivers. Silicon photonics (Si-Photonic) is one of the most promising techniques to realize tightly integrated optical transceivers for next-generation high speed I O standards. This dissertation focuses on the design techniques of...
    Resource Type:
    Dissertation
    Full Text:
    and Computer Engineering presented on September 15, 2016. Title: Design Techniques of High-Speed

  • Micropower incremental analog-to-digital converters

    Creator:
    Chen, Chia-Hung
    Abstract:
    Incremental ADCs (IADCs) have many advantages for low-frequency high-accuracy data conversion—they are easy to multiplex between channels, need simpler digital decimation filter, and allow extended counting with a Nyquist-rate ADC. A single-loop incremental ADC was designed and fabricated in 90 nm for a biosensor interface circuit. It incorporates one integrator,...
    Resource Type:
    Dissertation
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    .........................................................................................................3 2.2 The Analysis and Design of IADCs

  • Design of a 1.8-V 14-bit [delta] - [sigma] A/D converter with 8X oversampling and 4 MHz Nyquist output rate

    Creator:
    Jiang, Ruoxin
    Abstract:
    In this dissertation, a new Δ∑ A/D converter is presented that is ideally suited for communication applications. It is based on a single-loop single-stage structure, which can realize a high maximum out-of-band quantization noise gain while maintaining stable operation and thus achieve 14-bit resolution at 8 times oversampling. A fifth-order...
    Resource Type:
    Dissertation
    Full Text:
    Design of a 1.8-V 14-bit [delta] - [sigma] A/D converter

  • Low-power high-linearity digital-to-analog converters

    Creator:
    Kuo, Ming-Hung
    Abstract:
    In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC that has been...
    Resource Type:
    Masters Thesis
    Full Text:
    C. Temes In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog

  • Adaptive, wideband analog-to-digital conversion for convergent communication systems

    Creator:
    Batten, Robert D., 1973-
    Abstract:
    The exponential rate of advances in modern communication devices in the last several years have brought us higher levels of functionality and performance as well as reductions in physical size and power consumption. To continue this rate of advancement, next generation systems require wider bandwidth and higher resolution ADCs. Additionally,...
    Resource Type:
    Dissertation
    Full Text:
    design of analog-to-digital converters (ADCs), the front-end track-and-hold or sample-and-hold is often

  • A wideband low-power continuous-time delta-sigma modulator for next generation wireless applications

    Creator:
    Chen, Xuefeng
    Abstract:
    Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are widely used in wireless transceivers. Recently, continuous-time (CT) ΔΣ ADCs gain growing interest in wireless applications for their lower power consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts. In this thesis, a wideband low-power CT ΔΣ modulator for next generation...
    Resource Type:
    Dissertation
    Full Text:
    greatly benefited from his deep intuition and extensive knowledge of system and circuit design, from his

  • Low-power design techniques for low-voltage analog-to-digital converters

    Creator:
    Kim, Min Gyu
    Abstract:
    The demand for portable electronic systems and the continued down-scaling of device dimensions resulted in rapid improvement in the performance of integrated systems. Several low-voltage design techniques have been proposed to operate analog circuits with sub-1V supply. However, these techniques require higher power consumption to achieve large dynamic range while...
    Resource Type:
    Dissertation
    Full Text:
    Design Techniques for Low-Voltage Analog-to-Digital Converters. Abstract approved: Un-Ku Moon The

  • Design of a 14-bit continuous-time Delta-Sigma A/D modulator with 2.5MHz signal bandwidth

    Creator:
    Li, Zhimin
    Abstract:
    In recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Δ-Σ A/D converters for wideband wireless and wireline communication applications. So far no reported CT Δ-Σ A/D modulator achieves 14-bit or higher dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s)....
    Resource Type:
    Dissertation
    Full Text:
    and Computer Engineering presented on January 27, 2006. Title: Design of a 14-bit Continuous-Time

  • Design techniques for low power high speed successive approximation analog-to-digital converters

    Creator:
    Lin, Jiaming
    Abstract:
    This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the...
    Resource Type:
    Dissertation
    Full Text:
    Design Techniques for Low Power High Speed Successive

  • Techniques for improving timing accuracy of multi-gigahertz track/hold circuits

    Creator:
    Wang, Jingguang
    Abstract:
    Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC is limited by the timing accuracy of the sampling clock. A small sampling uncertainty can cause a large error in the sampled voltage and result...
    Resource Type:
    Masters Thesis
    Full Text:
      Figure 4-11 Non-overlap clocks 41  Figure 4-12 T/H circuit as a down-converter 42  Figure 5-1 Design