Search Constraints

Start Over
Filtering by: Creator Shillington, F. A. Remove constraint Creator: Shillington, F. A. Committee Member Moon, Un-Ku Remove constraint Committee Member: Moon, Un-Ku

Search Results

  • Compensation techniques for cascaded delta-sigma A/D converters and high-performance switched-capacitor circuits

    Creator:
    Sun, Tao
    Abstract:
    This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC circuits. A CDS technique...
    Resource Type:
    Dissertation
    Full Text:
    offset and finite opamp gain. Typically, the thermal noise has a wide frequency band, while the 1/f

  • A Wireless Energy Harvester for Powering Event-driven Internet-of-things Applications and Battery Charging

    Creator:
    Sadagopan, Kamala Raghavan
    Abstract:
    The need for sustainably powering unobtrusive internet-of-things applications has led to an interest in energy harvesting. Particularly, the proliferation of wireless communication and devices in the 2.4 GHz Industrial Scientific c Medical (ISM) band creates an opportunity to leverage commonly used devices for RF powering. This dissertation presents a low-quiescent-power...
    Resource Type:
    Dissertation
    Full Text:
    reduce minimum incident power to achieve targeted output voltage. 25 F ig u re 3. 2: A rc h it

  • A performance study of multithreading

    Creator:
    Kwak, Hantak
    Abstract:
    As the performance gap between processor and memory grows, memory latency will be a major bottleneck in achieving high processor utilization. Multithreading has emerged as one of the most promising and exciting techniques used to tolerate memory latency by exploiting thread-level parallelism. The question however remains as to how effective...
    Resource Type:
    Dissertation
    Full Text:
    A performance study of multithreading AN ABSTRACT OF THE

  • Design of a 14-bit continuous-time Delta-Sigma A/D modulator with 2.5MHz signal bandwidth

    Creator:
    Li, Zhimin
    Abstract:
    In recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Δ-Σ A/D converters for wideband wireless and wireline communication applications. So far no reported CT Δ-Σ A/D modulator achieves 14-bit or higher dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s)....
    Resource Type:
    Dissertation
    Full Text:
    f p ap er s CT DSM PAPERS ALL DSM PAPERS Figure 1.1 Number of papers on Δ-Σ A/D

  • Design of a 1.8-V 14-bit [delta] - [sigma] A/D converter with 8X oversampling and 4 MHz Nyquist output rate

    Creator:
    Jiang, Ruoxin
    Abstract:
    In this dissertation, a new Δ∑ A/D converter is presented that is ideally suited for communication applications. It is based on a single-loop single-stage structure, which can realize a high maximum out-of-band quantization noise gain while maintaining stable operation and thus achieve 14-bit resolution at 8 times oversampling. A fifth-order...
    Resource Type:
    Dissertation
    Full Text:
    converter with different input signal frequencies and a 32MHz clock, (a) f=500KHz, (b) f=1MHz. . . . 123

  • A wideband low-power continuous-time delta-sigma modulator for next generation wireless applications

    Creator:
    Chen, Xuefeng
    Abstract:
    Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are widely used in wireless transceivers. Recently, continuous-time (CT) ΔΣ ADCs gain growing interest in wireless applications for their lower power consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts. In this thesis, a wideband low-power CT ΔΣ modulator for next generation...
    Resource Type:
    Dissertation
    Full Text:
    of Philosophy in Electrical and Computer Engineering presented on March 15, 2007. Title: A

  • A Fully Integrated Bio-potential Low-noise Amplifier Utilizing Capacitor Multipliers

    Creator:
    Yong, OnnLim
    Abstract:
    In any biomedical signal acquisition system, a front-end amplifier is needed to amplify low amplitude bio-signals while filtering out any unwanted low-frequency artifacts. The design of low frequency poles within the sub-Hz range implies very large time-constants which goes against system integrability. In recent years, the pseudo resistor has been...
    Resource Type:
    Masters Thesis
    Full Text:
    . Oreggioni, A. A. Caputi and F. Silveira, "Current-efficient preamplifier architecture for CMRR sensitive

  • A dual-path 2-0 MASH ADC with dual digital error correction

    Creator:
    Zhang, Zhenyong
    Abstract:
    This dissertation presents a dual-path 2-0 MASH (Multi-stAge-noise -SHaping) ADC with two verified digital corrections of DAC mismatch error and quantization noise leakage. By using these two techniques, the requirements for the analog circuits are greatly relaxed. The dual-path structure generates two outputs, one only composed of conversion errors, the...
    Resource Type:
    Dissertation
    Full Text:
    Doctor of Philosophy in Electrical and Computer Engineering presented on November 27, 2006. Title: A

  • A new data encoding scheme for equalization - Integrated Pulse Width Modulation (iPWM)

    Creator:
    Ramachandran, Ashwin
    Abstract:
    This work presents a new data encoding scheme: Integrated Pulse Width Modulation (iPWM) for equalizing lossy wireline channels with the aim of achieving energy efficient wireline communication. The proposed scheme is able to overcome the fundamental limitations imposed by Manchester and Pulse Width Modulation (PWM) encoding on high data rate...
    Resource Type:
    Masters Thesis
    Full Text:
    -State Circuits, vol. 49, no. 12, pp. 3079–3090, Dec. 2015. [6] V. Stojanović, A. Ho, B. Garlepp, F

  • A digital multiplying delay locked loop for high frequency clock generation

    Creator:
    Uttarwar, Tushar
    Abstract:
    As Moore’s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks in such scaled processes is becoming a tough challenge. Digital phase locked loops (DPLLs) are being explored as an alternative to conventional analog PLLs but...
    Resource Type:
    Masters Thesis
    Full Text:
    stages produces a more symmetric waveform, and thus, lowers 1/f noise [13]. To achieve that goal, care