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Filtering by: Committee Member Nguyen, Thinh File Format application/pdf Non-Academic Affiliation Oregon State University. Graduate School Subject Registers (Computers)

1. Single-level dynamic register caching architecture for high-performance superscalar processors

Creator:: Liebert, John A.
Abstract:: The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
Resource Type:: Masters Thesis

2. Asymmetric clustering using a register cache

Creator:: Morrison, Roger Allen
Abstract:: Conventional register files spread porting resources uniformly across all registers. This paper proposes a method called Asymmetric Clustering using a Register Cache (ACRC). ACRC utilizes a fast register cache that concentrates valuable register file ports to the most active registers thereby reducing the total register file area and power consumption....
Resource Type:: Masters Thesis