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Filtering by: Alternative title ssim Report no. 74-16 Remove constraint Alternative title ssim: Report no. 74-16 Committee Member Nguyen, Thinh Remove constraint Committee Member: Nguyen, Thinh File Format application/pdf Remove constraint File Format: application/pdf

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  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    vary from 4 to 14. 16 was not used since then there would be no porting reduction, a major point of

  • Network coding in relay networks

    Creator:
    Alban, Eduardo
    Abstract:
    Transmission over wireless networks presents multiple technical challenges due to noise, interference, fading, power constraints and bandwidth limitation. Different solutions have been propposed to overcome these issues and some of them are treated here. Cooperative diversity has been proposed as an implementation for networks where terminals are restricted to using...
    Resource Type:
    Masters Thesis
    Full Text:
    Transmission . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.2 Multihop transmission

  • A genetic algorithm for the vehicle routing problem with heterogeneous vehicles from multiple depots, allowing multiple visits

    Creator:
    Lim, Hyunpae
    Abstract:
    In the thesis, an application of a genetic algorithm (GA) is considered to solve the vehicle routing problem (VRP) which involves heterogeneous vehicles to serve known customer demands from multiple depots achieving the minimum delivery cost, where each customer must be satisfied by one or more visit(s), and each vehicle...
    Resource Type:
    Masters Thesis
    Full Text:
    …………………………… 16 2.2.4 Selection ………………………………………………... 18 2.2.5 Crossover ………………………………………………. 20 2.2.6

  • Low-complexity high-speed VLSI design of low-density parity-check decoders

    Creator:
    Cui, Zhiqiang
    Abstract:
    Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g.,...
    Resource Type:
    Dissertation
    Full Text:
    for hardware implementation. The encoders of QC-LDPC codes can be built with shift-registers [16

  • A channelized digital receiver design for UWB sytems in a multipath indoor environment

    Creator:
    Chang, Yuhao
    Abstract:
    This thesis presents a channelized digital receiver design for UWB sytems in a multipath indoor environment. The UWB technology has been used for commercial and military purposes due to a number of advantages such as low-power consumption, noise-like and carrier free. The energy of UWB signal is spread over a...
    Resource Type:
    Masters Thesis
    Full Text:
    ……………...............................................................................................15 3.4 Conclusion…………… ……………………………………………………...16 4. Proposed System Design

  • Data processing for anomaly detection in web-based applications

    Creator:
    Gaarudapuram Sriraghavan, Rajagopal
    Abstract:
    Web applications are popular attack targets. Misuse detection systems use signature databases to detect known attacks. However, it is difficult to keep the database up to date with the rate of discovery of vulnerabilities. They also cannot detect zero-day attacks. By contrast, anomaly detection systems learn the normal behavior of...
    Resource Type:
    Masters Thesis
    Full Text:
    -paced or making no progress, he kept nudging me gently, and giving me advice to keep me going. Thanks

  • Channel estimation and data detection for mobile MIMO OFDM systems

    Creator:
    Gao, Jie
    Abstract:
    Designing spectral efficient, high-speed wireless links that offer high quality- of-service and range capability has been a critical research and engineering challenge. In this thesis, we mainly address the complexity and performance issues of channel estimation and data detection in multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) systems over...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3 SIC Detection

  • Asymmetric clustering using a register cache

    Creator:
    Morrison, Roger Allen
    Abstract:
    Conventional register files spread porting resources uniformly across all registers. This paper proposes a method called Asymmetric Clustering using a Register Cache (ACRC). ACRC utilizes a fast register cache that concentrates valuable register file ports to the most active registers thereby reducing the total register file area and power consumption....
    Resource Type:
    Masters Thesis
    Full Text:
    register access time and, therefore, branch misprediction penalty.............. 16 LIST OF TABLES

  • Gray codes and their applications

    Creator:
    Anantha, Madhusudhanan
    Abstract:
    An n-bit Gray code is an ordered set of all 2n binary strings of length n. The special property of this listing is that Hamming distance between consecutive vectors is exactly 1. If the last and first codeword also have a Hamming distance 1 then the code is said to...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.1 Constant Weight Codes . . . . . . . . . . . . . . . . . . . . . . 16 3.1.2 Berger Codes [5

  • Instruction fetching, scheduling, and forwarding in a dynamic multithreaded processor

    Creator:
    Browning, Adam W.
    Abstract:
    Dynamic multithreaded processors attempt to increase the performance of a single sequential program by dynamically extracting threads from sources such as loop iterations. The scheduling of instructions in such a processor plays a vital role in the amount of thread level parallelism that can be extracted and thus the overall...
    Resource Type:
    Masters Thesis
    Full Text:
    .............................................................................16 6: CIS in the DSMT architecture